From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32D091F1534; Fri, 11 Jul 2025 07:44:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752219842; cv=none; b=bOZcm8bqktb5Qrm3FPCWRbGAcLUG8Ag+xjMmB3a6nF+mzQedxiQ069hcfCdY1GnSNUoOTINfmuhbrtnzNZl6yvTVKhBq/eKCPCcdtt0qns+JEh4y/GljVRxS8o0Oof6jyniuqr7t+WHnjPvNiAt17AloyPRpjYaw1YGeY4b7bKc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752219842; c=relaxed/simple; bh=RLvV0rMPRETp8kXQ1/QLsAR0m2oC5br14HZ07aP+kLY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=bBe4jDVuQ0IUfbm3/ejwO128H+BPeITPS8k2EayXWQ2Crw2yV7Xr1BIdqrjf4Sm3YByXl5fSPcE2XGCA5NInZaZQQc3Nt21MU0YkPoVk4WWdAGijcYKRefjLvU/qnk63ITOY07UDmkkCVO0k3rNVV9LKB+IbnIz8UX0yaIULS5o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=05Z7EaRf; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="05Z7EaRf" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56B30ckx014453; Fri, 11 Jul 2025 09:43:38 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= vCMmTABrSBqeAhv7e77caexkaudNwZFg/B0FOzQ1fiU=; b=05Z7EaRfhT7myXFk wytVQoJhBlgAdS7ffz9ZcQJXkIjfVi8O6VgkZHi+n/FDbvNdZFmABzYrE/ROdl7T EvIY77AITnLvybk3haIHyYTae45do3P2lcR3/wI4CBvixZCNmsWWHkvjMeKm9+vb WG0eCX5e0mSgWn4iDHpBSekRQckMJ/9xf9rcHhiVuxvpXtuOXnIkM8tAzvDBlCpp EMRpsMRVyzieUDuVkRyCNoIr9sWTVpEoVOzYo4eKkfuDUpSare5b7M2nIKMgPbz7 TbN4Bvtt9X+OL1NmyBcyqtdma1KFQwo4dLVCMeJPy3VHsOEkDT77F94UO7u0+AUF oJ0H1g== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 47qdm6arhn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Jul 2025 09:43:38 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D536B40049; Fri, 11 Jul 2025 09:42:26 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6CD83B11278; Fri, 11 Jul 2025 09:41:42 +0200 (CEST) Received: from localhost (10.252.16.187) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 11 Jul 2025 09:41:42 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Fri, 11 Jul 2025 09:41:24 +0200 Subject: [PATCH v7 6/8] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp25 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-ID: <20250711-hdp-upstream-v7-6-faeecf7aaee1@foss.st.com> References: <20250711-hdp-upstream-v7-0-faeecf7aaee1@foss.st.com> In-Reply-To: <20250711-hdp-upstream-v7-0-faeecf7aaee1@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski , Antonio Borneo , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-7616d X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-11_02,2025-07-09_01,2025-03-28_01 Add the hdp devicetree node for stm32mp25 SoC family Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 8d87865850a7..fa2b6a1881f2 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1148,6 +1148,13 @@ package_otp@1e8 { }; }; + hdp: pinctrl@44090000 { + compatible = "st,stm32mp251-hdp"; + reg = <0x44090000 0x400>; + clocks = <&rcc CK_BUS_HDP>; + status = "disabled"; + }; + rcc: clock-controller@44200000 { compatible = "st,stm32mp25-rcc"; reg = <0x44200000 0x10000>; -- 2.43.0