From: Rob Herring <robh@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
cros-qcom-dts-watchers@chromium.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node
Date: Tue, 15 Jul 2025 16:59:25 -0500 [thread overview]
Message-ID: <20250715215925.GA2084021-robh@kernel.org> (raw)
In-Reply-To: <20250105101612.t6c4pw5uxhb5rdde@thinkpad>
On Sun, Jan 05, 2025 at 03:46:12PM +0530, Manivannan Sadhasivam wrote:
> Hi Bjorn,
>
> On Fri, Jan 03, 2025 at 03:05:31PM -0600, Bjorn Helgaas wrote:
> > On Thu, Mar 21, 2024 at 04:46:21PM +0530, Manivannan Sadhasivam wrote:
> > > On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> > > for each controller instance. Hence, add a node to represent the bridge.
> > >
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > > arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++++++++++++++++++++
> > > 1 file changed, 30 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > > index 39bd8f0eba1e..fe5485256b22 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > > @@ -2203,6 +2203,16 @@ pcie0: pcie@1c00000 {
> > > dma-coherent;
> > >
> > > status = "disabled";
> > > +
> > > + pcie@0 {
> > > + device_type = "pci";
> > > + reg = <0x0 0x0 0x0 0x0 0x0>;
> > > + bus-range = <0x01 0xff>;
> >
> > Hi Mani, most or all of the patches in this series add this
> > "bus-range" property. IIUC, these are all Root Ports and hence the
> > secondary/subordinate bus numbers should be programmable.
> >
>
> Right. It is not a functional dependency.
>
> > If that's the case, I don't think we need to include "bus-range" in DT
> > for them, do we?
> >
>
> We mostly include it to silence the below bindings check for the endpoint device
> node:
>
> Warning (pci_device_bus_num): /soc@0/pcie@1c00000/pcie@0/wifi@0: PCI bus number 1 out of range, expected (0 - 0)
The mistake is using bus number 1 instead of 0.
> DTC check is happy if the 'bus-range' property is absent in the bridge node. But
> while validating the endpoint node (if defined), it currently relies on the
> parent 'bus-range' property to verify the bus number provided in the endpoint
> 'reg' property.
>
> I don't know else the check can verify the correctness of the endpoint bus
> number. So deferring to Rob here.
Sorry I'm late to the party, but found this from another thread
today[1]. More details there.
You should not have 'bus-range' at all in your DT and the bus for every
BDF address should be 0. You only need 'bus-range' if your h/w is
broken.
Rob
[1] https://lore.kernel.org/all/CAL_Jsq+z+5_=YXiyCW1sbKDe0cjGNG7Qk=uRQ3efAFTd1J2ayQ@mail.gmail.com/
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2025-07-15 21:59 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-21 11:16 [PATCH v2 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node Manivannan Sadhasivam
2025-01-03 21:05 ` Bjorn Helgaas
2025-01-05 10:16 ` Manivannan Sadhasivam
2025-01-06 23:07 ` Bjorn Helgaas
2025-01-15 10:54 ` Manivannan Sadhasivam
2025-01-15 17:42 ` Bjorn Helgaas
2025-01-15 17:59 ` Manivannan Sadhasivam
2025-01-15 18:13 ` Bjorn Helgaas
2025-01-19 15:25 ` Manivannan Sadhasivam
2025-01-21 23:11 ` Bjorn Helgaas
2025-01-28 13:45 ` Manivannan Sadhasivam
2025-01-28 16:16 ` Bjorn Helgaas
2025-02-07 16:53 ` Manivannan Sadhasivam
2025-07-15 21:59 ` Rob Herring [this message]
2024-03-21 11:16 ` [PATCH v2 02/21] arm64: dts: qcom: sdm845: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 03/21] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 04/21] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 05/21] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 06/21] arm64: dts: qcom: sm8550: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 07/21] arm64: dts: qcom: sm8650: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 08/21] arm64: dts: qcom: sa8775p: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 09/21] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 10/21] arm64: dts: qcom: msm8998: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 11/21] arm64: dts: qcom: sc7280: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 12/21] arm64: dts: qcom: qcs404: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 13/21] arm64: dts: qcom: sc8180x: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 14/21] arm64: dts: qcom: msm8996: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 15/21] arm64: dts: qcom: ipq8074: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 16/21] arm64: dts: qcom: ipq6018: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 17/21] ARM: dts: qcom: ipq8064: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 18/21] ARM: dts: qcom: ipq4019: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 19/21] ARM: dts: qcom: apq8064: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 20/21] ARM: dts: qcom: sdx55: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci" Manivannan Sadhasivam
2024-03-23 0:11 ` [PATCH v2 00/21] Add PCIe bridge node in DT for Qcom SoCs Konrad Dybcio
2024-04-21 22:29 ` (subset) " Bjorn Andersson
2024-05-27 3:00 ` Bjorn Andersson
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