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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b3bbe6bd8f8sm13912054a12.38.2025.07.16.08.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jul 2025 08:20:42 -0700 (PDT) From: Pankaj Patil To: sboyd@kernel.org, mturquette@baylibre.com, andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_rjendra@quicinc.com, taniya.das@oss.qualcomm.com Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] clk: qcom: rpmh: Add support for Glymur rpmh clocks Date: Wed, 16 Jul 2025 20:50:14 +0530 Message-Id: <20250716152017.4070029-5-pankaj.patil@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com> References: <20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=dKimmPZb c=1 sm=1 tr=0 ts=6877c34c cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=RRvC4NyyfoRIYhV0TvUA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: zfvn_bCFBxqL4zMsrI9TusN0OTJv38B1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE2MDEzOCBTYWx0ZWRfX6WTNqklzxPPV mZHMvStzZDBIraO9+ho9Fw2F7sR7cFamIZVboESs30RyYNHgxlCcf9+Q4wX2DlGf7DqsXnXhSJX 79qUVz3vkKOYUrtrp27Nd9zniTaQgRxw0fQ1EWP8LrO14+R4oSogSGfMTFVilddt0dRfPKk9ztI FWjJEbGNRiyvO1vgfDSCnDjcOhyUcovjdb4hxeO12CNU6XylYfn7EOuWkaNT5Noays9g92xc4XE UXZa3vYysTNfQAy9bL0LudQjTvwDJCwF3uy1F7250j+hF4wzjTtqYKrzZK7NYs6ewTxJmvLyemQ KTfZYRKFS94fm58vBEYsO+xzTY/wGPKUAujxpz/g6MxxWhXtHzhowzv0DsyT02nS9oG4pgk8Ib4 GFEhLrubedWNgWh+sAtD8gm0iivL4xtHm9GkRyOE7M0P8dZA/w29YmrOvYL7V0acmmVRRGde X-Proofpoint-ORIG-GUID: zfvn_bCFBxqL4zMsrI9TusN0OTJv38B1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-16_02,2025-07-16_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507160138 From: Taniya Das Add RPMH clock support for the Glymur SoC to enable proper clock management. Signed-off-by: Taniya Das Signed-off-by: Pankaj Patil --- drivers/clk/qcom/clk-rpmh.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 00fb3e53a388..1bc1333087b4 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -388,6 +388,11 @@ DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); +DEFINE_CLK_RPMH_VRM(clk3, _a, "C3A_E0", 1); +DEFINE_CLK_RPMH_VRM(clk4, _a, "C4A_E0", 1); +DEFINE_CLK_RPMH_VRM(clk5, _a, "C5A_E0", 1); +DEFINE_CLK_RPMH_VRM(clk8, _a, "C8A_E0", 1); + DEFINE_CLK_RPMH_BCM(ce, "CE0"); DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); DEFINE_CLK_RPMH_BCM(ipa, "IP0"); @@ -854,6 +859,22 @@ static const struct clk_rpmh_desc clk_rpmh_sm8750 = { .clka_optional = true, }; +static struct clk_hw *glymur_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_clk3_a.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_clk4_a.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a_ao.hw, + [RPMH_RF_CLK5] = &clk_rpmh_clk5_a.hw, + [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_glymur = { + .clks = glymur_rpmh_clocks, + .num_clks = ARRAY_SIZE(glymur_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -943,6 +964,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) } static const struct of_device_id clk_rpmh_match_table[] = { + { .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur}, { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615}, { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, -- 2.34.1