* [PATCH 3/4] ARM: dts: sti: extract display subsystem out of soc
2025-07-17 19:15 [PATCH 0/4] STi device-tree display subsystem rework Raphael Gallais-Pou
2025-07-17 19:15 ` [PATCH 1/4] drm/sti: check dma_set_coherent_mask return value Raphael Gallais-Pou
2025-07-17 19:15 ` [PATCH 2/4] drm/sti: make use of drm_of_component_probe Raphael Gallais-Pou
@ 2025-07-17 19:15 ` Raphael Gallais-Pou
2025-07-17 19:15 ` [PATCH 4/4] ARM: dts: sti: remove useless cells fields Raphael Gallais-Pou
2025-07-20 23:06 ` [PATCH 0/4] STi device-tree display subsystem rework Rob Herring (Arm)
4 siblings, 0 replies; 6+ messages in thread
From: Raphael Gallais-Pou @ 2025-07-17 19:15 UTC (permalink / raw)
To: Alain Volmat, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Simona Vetter, Patrice Chotard, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: dri-devel, linux-kernel, linux-arm-kernel, devicetree
The display subsystem represent how IPs are interacting together and
have nothing to do within the SoC node.
Extract it from the SoC node and let IPs nodes in the Soc node.
Several nodes did not use conventional name:
* sti-display-subsystem -> display-subsystem
* sti-controller -> display-controller
* sti-tvout -> encoder
* sti-hda -> analog
* sti-hqvdp -> plane
Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com>
---
arch/arm/boot/dts/st/stih410.dtsi | 316 +++++++++++++++++++++++---------------
1 file changed, 188 insertions(+), 128 deletions(-)
diff --git a/arch/arm/boot/dts/st/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi
index d56343f44fda4e9e1de2e5efc86e2d984bad14b4..47d66d7eb07a3d73d98b3e21d62b2253aa1171e4 100644
--- a/arch/arm/boot/dts/st/stih410.dtsi
+++ b/arch/arm/boot/dts/st/stih410.dtsi
@@ -34,6 +34,41 @@ usb2_picophy2: phy3 {
status = "disabled";
};
+ display-subsystem {
+ compatible = "st,sti-display-subsystem";
+ ports = <&compositor>, <&hqvdp>, <&tvout>, <&sti_hdmi>;
+
+ assigned-clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_c0_flexgen CLK_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP1>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP2>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP3>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP4>;
+
+ assigned-clock-parents = <0>,
+ <0>,
+ <0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>;
+
+ assigned-clock-rates = <297000000>,
+ <297000000>,
+ <0>,
+ <400000000>,
+ <400000000>;
+ };
+
soc {
ohci0: usb@9a03c00 {
compatible = "st,st-ohci-300x";
@@ -99,153 +134,178 @@ ehci1: usb@9a83e00 {
status = "disabled";
};
- sti-display-subsystem@0 {
- compatible = "st,sti-display-subsystem";
+ compositor: display-controller@9d11000 {
+ compatible = "st,stih407-compositor";
+ reg = <0x9d11000 0x1000>;
+
+ clock-names = "compo_main",
+ "compo_aux",
+ "pix_main",
+ "pix_aux",
+ "pix_gdp1",
+ "pix_gdp2",
+ "pix_gdp3",
+ "pix_gdp4",
+ "main_parent",
+ "aux_parent";
+
+ clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP1>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP2>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP3>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP4>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>;
+
+ reset-names = "compo-main", "compo-aux";
+ resets = <&softreset STIH407_COMPO_SOFTRESET>,
+ <&softreset STIH407_COMPO_SOFTRESET>;
+ st,vtg = <&vtg_main>, <&vtg_aux>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ compo_main_out: endpoint {
+ remote-endpoint = <&tvout_in0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ compo_aux_out: endpoint {
+ remote-endpoint = <&tvout_in1>;
+ };
+ };
+ };
+ };
+
+ tvout: encoder@8d08000 {
+ compatible = "st,stih407-tvout";
+ reg = <0x8d08000 0x1000>;
+ reg-names = "tvout-reg";
+ reset-names = "tvout";
+ resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
#address-cells = <1>;
#size-cells = <1>;
+ assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
+ <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
+ <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
+ <&clk_s_d0_flexgen CLK_PCM_0>,
+ <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
+ <&clk_s_d2_flexgen CLK_HDDAC>;
- reg = <0 0>;
- assigned-clocks = <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_flexgen CLK_COMPO_DVP>,
- <&clk_s_c0_flexgen CLK_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_GDP1>,
- <&clk_s_d2_flexgen CLK_PIX_GDP2>,
- <&clk_s_d2_flexgen CLK_PIX_GDP3>,
- <&clk_s_d2_flexgen CLK_PIX_GDP4>;
-
- assigned-clock-parents = <0>,
- <0>,
- <0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_c0_pll1 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>,
- <&clk_s_d2_quadfs 0>,
+ assigned-clock-parents = <&clk_s_d2_quadfs 0>,
+ <&clk_tmdsout_hdmi>,
<&clk_s_d2_quadfs 0>,
+ <&clk_s_d0_quadfs 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>;
- assigned-clock-rates = <297000000>,
- <297000000>,
- <0>,
- <400000000>,
- <400000000>;
-
- ranges;
-
- sti-compositor@9d11000 {
- compatible = "st,stih407-compositor";
- reg = <0x9d11000 0x1000>;
-
- clock-names = "compo_main",
- "compo_aux",
- "pix_main",
- "pix_aux",
- "pix_gdp1",
- "pix_gdp2",
- "pix_gdp3",
- "pix_gdp4",
- "main_parent",
- "aux_parent";
-
- clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
- <&clk_s_c0_flexgen CLK_COMPO_DVP>,
- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_GDP1>,
- <&clk_s_d2_flexgen CLK_PIX_GDP2>,
- <&clk_s_d2_flexgen CLK_PIX_GDP3>,
- <&clk_s_d2_flexgen CLK_PIX_GDP4>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
-
- reset-names = "compo-main", "compo-aux";
- resets = <&softreset STIH407_COMPO_SOFTRESET>,
- <&softreset STIH407_COMPO_SOFTRESET>;
- st,vtg = <&vtg_main>, <&vtg_aux>;
- };
-
- sti-tvout@8d08000 {
- compatible = "st,stih407-tvout";
- reg = <0x8d08000 0x1000>;
- reg-names = "tvout-reg";
- reset-names = "tvout";
- resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
+ ports {
#address-cells = <1>;
- #size-cells = <1>;
- assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
- <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
- <&clk_s_d0_flexgen CLK_PCM_0>,
- <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
- <&clk_s_d2_flexgen CLK_HDDAC>;
+ #size-cells = <0>;
- assigned-clock-parents = <&clk_s_d2_quadfs 0>,
- <&clk_tmdsout_hdmi>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d0_quadfs 0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 0>;
+ port@0 {
+ reg = <0>;
+ tvout_in0: endpoint {
+ remote-endpoint = <&compo_main_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ tvout_in1: endpoint {
+ remote-endpoint = <&compo_aux_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ tvout_out0: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ tvout_out1: endpoint {
+ remote-endpoint = <&hda_in>;
+ };
+ };
};
+ };
- sti_hdmi: sti-hdmi@8d04000 {
- compatible = "st,stih407-hdmi";
- reg = <0x8d04000 0x1000>;
- reg-names = "hdmi-reg";
- #sound-dai-cells = <0>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq";
- clock-names = "pix",
- "tmds",
- "phy",
- "audio",
- "main_parent",
- "aux_parent";
+ sti_hdmi: hdmi@8d04000 {
+ compatible = "st,stih407-hdmi";
+ reg = <0x8d04000 0x1000>;
+ reg-names = "hdmi-reg";
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq";
+ clock-names = "pix",
+ "tmds",
+ "phy",
+ "audio",
+ "main_parent",
+ "aux_parent";
- clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
- <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
- <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
- <&clk_s_d0_flexgen CLK_PCM_0>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
+ clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
+ <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
+ <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
+ <&clk_s_d0_flexgen CLK_PCM_0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>;
- hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
- reset-names = "hdmi";
- resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
- ddc = <&hdmiddc>;
+ hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
+ reset-names = "hdmi";
+ resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
+ ddc = <&hdmiddc>;
+
+ port {
+ hdmi_in: endpoint {
+ remote-endpoint = <&tvout_out0>;
+ };
};
+ };
- sti-hda@8d02000 {
- compatible = "st,stih407-hda";
- status = "disabled";
- reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
- reg-names = "hda-reg", "video-dacs-ctrl";
- clock-names = "pix",
- "hddac",
- "main_parent",
- "aux_parent";
- clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
- <&clk_s_d2_flexgen CLK_HDDAC>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
- };
+ analog@8d02000 {
+ compatible = "st,stih407-hda";
+ status = "disabled";
+ reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
+ reg-names = "hda-reg", "video-dacs-ctrl";
+ clock-names = "pix",
+ "hddac",
+ "main_parent",
+ "aux_parent";
+ clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
+ <&clk_s_d2_flexgen CLK_HDDAC>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>;
- sti-hqvdp@9c00000 {
- compatible = "st,stih407-hqvdp";
- reg = <0x9C00000 0x100000>;
- clock-names = "hqvdp", "pix_main";
- clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
- <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
- reset-names = "hqvdp";
- resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
- st,vtg = <&vtg_main>;
+ port {
+ hda_in: endpoint {
+ remote-endpoint = <&tvout_out1>;
+ };
};
};
+ hqvdp: plane@9c00000 {
+ compatible = "st,stih407-hqvdp";
+ reg = <0x9C00000 0x100000>;
+ clock-names = "hqvdp", "pix_main";
+ clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
+ reset-names = "hqvdp";
+ resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
+ st,vtg = <&vtg_main>;
+ };
+
bdisp0:bdisp@9f10000 {
compatible = "st,stih407-bdisp";
reg = <0x9f10000 0x1000>;
--
2.50.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 0/4] STi device-tree display subsystem rework
2025-07-17 19:15 [PATCH 0/4] STi device-tree display subsystem rework Raphael Gallais-Pou
` (3 preceding siblings ...)
2025-07-17 19:15 ` [PATCH 4/4] ARM: dts: sti: remove useless cells fields Raphael Gallais-Pou
@ 2025-07-20 23:06 ` Rob Herring (Arm)
4 siblings, 0 replies; 6+ messages in thread
From: Rob Herring (Arm) @ 2025-07-20 23:06 UTC (permalink / raw)
To: Raphael Gallais-Pou
Cc: devicetree, dri-devel, linux-arm-kernel, Maxime Ripard,
linux-kernel, Alain Volmat, Conor Dooley, Simona Vetter,
Maarten Lankhorst, Krzysztof Kozlowski, David Airlie,
Patrice Chotard, Thomas Zimmermann
On Thu, 17 Jul 2025 21:15:31 +0200, Raphael Gallais-Pou wrote:
> This serie aims to rework the display-subsystem node, which was
> previously included directly within the SoC node. This was wrong
> because it is an abstraction and describes how IPs behave together, not
> what the hardware is. Instead, extract display-subsystem outside of the
> SoC node, and let IPs describe their connections. Doing so helps the
> readability, and eases the understanding of the hardware.
>
> Several nodes have been renamed to stick to the generic names defined in
> the device-tree specification.
>
> This series depends on another sent a few days ago. It is not critical
> though, since not having it only triggers warnings when building
> deprecated device-trees. Please see link below.
>
> Link: https://lore.kernel.org/lkml/20250714-sti-rework-v2-0-f4274920858b@gmail.com
>
> Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com>
> ---
> Raphael Gallais-Pou (4):
> drm/sti: check dma_set_coherent_mask return value
> drm/sti: make use of drm_of_component_probe
> ARM: dts: sti: extract display subsystem out of soc
> ARM: dts: sti: remove useless cells fields
>
> arch/arm/boot/dts/st/stih410.dtsi | 316 ++++++++++++++++++++++----------------
> drivers/gpu/drm/sti/sti_drv.c | 18 +--
> 2 files changed, 192 insertions(+), 142 deletions(-)
> ---
> base-commit: b9a572f471993d3e8bf874fcb57f331d66650440
> change-id: 20250401-sti-rework-b009551a362c
>
> Best regards,
> --
> Raphael Gallais-Pou <rgallaispou@gmail.com>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: base-commit b9a572f471993d3e8bf874fcb57f331d66650440 not known, ignoring
Base: attempting to guess base-commit...
Base: tags/v6.16-rc1-11-g2436e190bbdd (exact match)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/st/' for 20250717-sti-rework-v1-0-46d516fb1ebb@gmail.com:
arch/arm/boot/dts/st/stih410-b2120.dtb: soc (simple-bus): sti-display-subsystem@0: 'anyOf' conditional failed, one must be fixed:
'reg' is a required property
'ranges' is a required property
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
arch/arm/boot/dts/st/stih410-b2120.dtb: /soc/display-controller@9d11000: failed to match any schema with compatible: ['st,stih407-compositor']
arch/arm/boot/dts/st/stih410-b2120.dtb: /soc/encoder@8d08000: failed to match any schema with compatible: ['st,stih407-tvout']
arch/arm/boot/dts/st/stih410-b2120.dtb: encoder@8d08000 (st,stih407-tvout): 'anyOf' conditional failed, one must be fixed:
'clocks' is a required property
'#clock-cells' is a required property
from schema $id: http://devicetree.org/schemas/clock/clock.yaml#
arch/arm/boot/dts/st/stih410-b2120.dtb: /soc/hdmi@8d04000: failed to match any schema with compatible: ['st,stih407-hdmi']
arch/arm/boot/dts/st/stih410-b2260.dtb: /soc/display-controller@9d11000: failed to match any schema with compatible: ['st,stih407-compositor']
arch/arm/boot/dts/st/stih410-b2120.dtb: /soc/analog@8d02000: failed to match any schema with compatible: ['st,stih407-hda']
arch/arm/boot/dts/st/stih410-b2120.dtb: /soc/plane@9c00000: failed to match any schema with compatible: ['st,stih407-hqvdp']
arch/arm/boot/dts/st/stih410-b2260.dtb: /soc/encoder@8d08000: failed to match any schema with compatible: ['st,stih407-tvout']
arch/arm/boot/dts/st/stih410-b2260.dtb: encoder@8d08000 (st,stih407-tvout): 'anyOf' conditional failed, one must be fixed:
'clocks' is a required property
'#clock-cells' is a required property
from schema $id: http://devicetree.org/schemas/clock/clock.yaml#
arch/arm/boot/dts/st/stih410-b2260.dtb: /soc/hdmi@8d04000: failed to match any schema with compatible: ['st,stih407-hdmi']
arch/arm/boot/dts/st/stih410-b2260.dtb: /soc/analog@8d02000: failed to match any schema with compatible: ['st,stih407-hda']
arch/arm/boot/dts/st/stih410-b2260.dtb: /soc/plane@9c00000: failed to match any schema with compatible: ['st,stih407-hqvdp']
arch/arm/boot/dts/st/stih410-b2120.dtb: /display-subsystem: failed to match any schema with compatible: ['st,sti-display-subsystem']
arch/arm/boot/dts/st/stih410-b2120.dtb: display-subsystem (st,sti-display-subsystem): 'anyOf' conditional failed, one must be fixed:
'clocks' is a required property
'#clock-cells' is a required property
from schema $id: http://devicetree.org/schemas/clock/clock.yaml#
arch/arm/boot/dts/st/stih410-b2260.dtb: /display-subsystem: failed to match any schema with compatible: ['st,sti-display-subsystem']
arch/arm/boot/dts/st/stih410-b2260.dtb: display-subsystem (st,sti-display-subsystem): 'anyOf' conditional failed, one must be fixed:
'clocks' is a required property
'#clock-cells' is a required property
from schema $id: http://devicetree.org/schemas/clock/clock.yaml#
^ permalink raw reply [flat|nested] 6+ messages in thread