* [PATCH v5 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189
2025-07-18 7:56 [PATCH v5 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang
@ 2025-07-18 7:56 ` Sirius Wang
2025-07-18 7:56 ` [PATCH v5 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189 Sirius Wang
2025-07-18 7:56 ` [PATCH v5 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile Sirius Wang
2 siblings, 0 replies; 4+ messages in thread
From: Sirius Wang @ 2025-07-18 7:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Jiri Slaby, Matthias Brugger,
AngeloGioacchino Del Regno, Sean Wang
Cc: devicetree, linux-kernel, linux-serial, linux-arm-kernel,
linux-mediatek, wenst, xavier.chang, Sirius Wang
This commit adds dt-binding documentation for the MediaTek MT8189
reference board.
Signed-off-by: Sirius Wang <sirius.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 19ed9448c9c2..5052b6b2dcce 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -382,6 +382,10 @@ properties:
- enum:
- mediatek,mt8188-evb
- const: mediatek,mt8188
+ - items:
+ - enum:
+ - mediatek,mt8189-evb
+ - const: mediatek,mt8189
- description: Google Hayato
items:
- const: google,hayato-rev1
--
2.45.2
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v5 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189
2025-07-18 7:56 [PATCH v5 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang
2025-07-18 7:56 ` [PATCH v5 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189 Sirius Wang
@ 2025-07-18 7:56 ` Sirius Wang
2025-07-18 7:56 ` [PATCH v5 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile Sirius Wang
2 siblings, 0 replies; 4+ messages in thread
From: Sirius Wang @ 2025-07-18 7:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Jiri Slaby, Matthias Brugger,
AngeloGioacchino Del Regno, Sean Wang
Cc: devicetree, linux-kernel, linux-serial, linux-arm-kernel,
linux-mediatek, wenst, xavier.chang, Sirius Wang, Conor Dooley
Add compatible string for serial on MT8189 SoC.
Signed-off-by: Sirius Wang <sirius.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
index 5bd8a8853ae0..3f0f4aea0a4c 100644
--- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
@@ -47,6 +47,7 @@ properties:
- mediatek,mt8183-uart
- mediatek,mt8186-uart
- mediatek,mt8188-uart
+ - mediatek,mt8189-uart
- mediatek,mt8192-uart
- mediatek,mt8195-uart
- mediatek,mt8365-uart
--
2.45.2
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v5 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
2025-07-18 7:56 [PATCH v5 0/3] Add mt8189 dts evaluation board and Makefile Sirius Wang
2025-07-18 7:56 ` [PATCH v5 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189 Sirius Wang
2025-07-18 7:56 ` [PATCH v5 2/3] dt-bindings: serial: mediatek,uart: Add compatible for MT8189 Sirius Wang
@ 2025-07-18 7:56 ` Sirius Wang
2 siblings, 0 replies; 4+ messages in thread
From: Sirius Wang @ 2025-07-18 7:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Jiri Slaby, Matthias Brugger,
AngeloGioacchino Del Regno, Sean Wang
Cc: devicetree, linux-kernel, linux-serial, linux-arm-kernel,
linux-mediatek, wenst, xavier.chang, Sirius Wang
Add mt8189 dts evaluation board and Mafefile
Signed-off-by: Sirius Wang <sirius.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 ++
arch/arm64/boot/dts/mediatek/mt8189.dtsi | 375 ++++++++++++++++++++
3 files changed, 396 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index a4df4c21399e..52c5b799308e 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
new file mode 100644
index 000000000000..e5d9ce1b8e61
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Sirius Wang <sirius.wang@mediatek.com>
+ */
+/dts-v1/;
+#include "mt8189.dtsi"
+
+/ {
+ model = "MediaTek MT8189 evaluation board";
+ compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
+
+ chosen: chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
new file mode 100644
index 000000000000..2444c3e553ec
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "mediatek,mt8189";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ clk32k: oscillator-clk32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "clk32k";
+ };
+
+ clk13m: oscillator-clk13m {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clk26m>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ clock-output-names = "clk13m";
+ };
+
+ clk26m: oscillator-clk26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk104m: oscillator-clk104m {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clk26m>;
+ clock-mult = <4>;
+ clock-div = <1>;
+ clock-output-names = "clk104m";
+ };
+
+ ulposc: oscillator-ulposc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <520000000>;
+ clock-output-names = "ulposc";
+ };
+
+ ulposc3: oscillator-ulposc3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "ulposc3";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <3000000000>;
+ capacity-dmips-mhz = <958>;
+ cpu-idle-states = <&cpu_off_b>, <&cpu_s2idle>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <3000000000>;
+ capacity-dmips-mhz = <958>;
+ cpu-idle-states = <&cpu_off_b>, <&cpu_s2idle>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ core4 {
+ cpu = <&cpu4>;
+ };
+ core5 {
+ cpu = <&cpu5>;
+ };
+ core6 {
+ cpu = <&cpu6>;
+ };
+ core7 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_off_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <25>;
+ exit-latency-us = <57>;
+ min-residency-us = <5700>;
+ };
+
+ cpu_off_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <35>;
+ exit-latency-us = <82>;
+ min-residency-us = <1890>;
+ };
+
+ cpu_s2idle: cpu-s2idle {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x020180ff>;
+ local-timer-stop;
+ entry-latency-us = <10000>;
+ exit-latency-us = <10000>;
+ min-residency-us = <4294967295>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+ };
+
+ memory: memory@40000000 {
+ device_type = "memory";
+ /* This memory size is filled in by the bootloader */
+ reg = <0 0x40000000 0 0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0xc000000 0 0x40000>, /* distributor */
+ <0 0xc040000 0 0x200000>; /* redistributor */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu6 &cpu7>;
+ };
+ };
+ };
+
+ uart0: serial@11001000 {
+ compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001000 0 0x1000>;
+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+ };
+};
--
2.45.2
^ permalink raw reply related [flat|nested] 4+ messages in thread