[PATCH RFC 00/10] riscv: Add initial support for Anlogic DR1V90

[PATCH RFC 00/10] riscv: Add initial support for Anlogic DR1V90

[Junhui Liu]

This patch series introduces initial support for the Anlogic DR1V90 SoC
[1] and the Milianke MLKPAI-FS01 [2] board.

The DR1V90 is a RISC-V based FPSoC from Anlogic, featuring a Nuclei
UX900 [3] core as its processing system (PS) and 94,464 LUTs in the
programmable logic (PL) part. The Milianke MLKPAI-FS01 board is one of
the first platforms based on this SoC, with UART1 routed to a Type-C
interface for console access.

Tested upon Milianke MLKPAI-FS01 board based on vendor's OpenSBI and
U-Boot with log [4]. The log indicates that OpenSBI is running at
0x3fe00000. Since the region 0x20000000-0x3fffffff is a mirror of
0x00000000-0x1fffffff, the actual physical base address for OpenSBI is
0x1fe00000.

Notice: A "no4lvl" bootarg is currently required for successful boot on
the DR1V90 platform, since the SoC hangs if the kernel attempts to use
unsupported 4-level or 5-level paging modes. I plan to submit a
follow-up patch to allow the kernel to query the supported MMU mode
directly from the "mmu-type" property in the device tree, to avoid
probing unsupported SATP modes.

This patch series is marked as RFC because basic drivers such as clock,
reset and pinctrl are not yet supported. These essential drivers will be
submitted in later patch series.

Link: https://www.anlogic.com/product/fpga/saldragon/dr1 [1]
Link: https://www.milianke.com/product-item-104.html [2]
Link: https://nucleisys.com/product/900.php [3]
Link: https://gist.github.com/pigmoral/7a61297593386dadbf357837d93adc95 [4]
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
Junhui Liu (10):
      dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
      dt-bindings: riscv: Add Nuclei UX900 compatibles
      dt-bindings: riscv: Add Anlogic DR1V90
      dt-bindings: timer: Add Anlogic DR1V90 CLINT
      dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
      dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
      riscv: Add Anlogic SoC famly Kconfig support
      riscv: dts: Add initial Anlogic DR1V90 SoC device tree
      riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
      riscv: defconfig: Enable Anlogic SoC

 .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
 .../devicetree/bindings/riscv/anlogic.yaml         | 27 +++++++
 Documentation/devicetree/bindings/riscv/cpus.yaml  |  1 +
 .../bindings/serial/snps-dw-apb-uart.yaml          |  1 +
 .../devicetree/bindings/timer/sifive,clint.yaml    |  1 +
 .../devicetree/bindings/vendor-prefixes.yaml       |  6 ++
 arch/riscv/Kconfig.socs                            |  5 ++
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/anlogic/Makefile               |  2 +
 arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 +++++++
 arch/riscv/boot/dts/anlogic/dr1v90.dtsi            | 86 ++++++++++++++++++++++
 arch/riscv/configs/defconfig                       |  1 +
 12 files changed, 160 insertions(+)
---
base-commit: 89be9a83ccf1f88522317ce02f854f30d6115c41
change-id: 20250710-dr1v90-basic-dt-352e9ae5acb8

Best regards,
-- 
Junhui Liu <junhui.liu@pigmoral.tech>

[PATCH RFC 01/10] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei

[Junhui Liu]

Add vendor prefixes for "anlogic", "milianke" and "nuclei". These are
required for describing the Milianke MLKPAI-FS01 board with DR1V90 SoC
from Anlogic, which uses a processor core designed by Nuclei.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 5d2a7a8d3ac6c666c8b557c2ef385918e5e97bf9..6ace3c66ce58fc15ef7cc70e88fd1904cb8395b9 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -127,6 +127,8 @@ patternProperties:
     description: Anbernic
   "^andestech,.*":
     description: Andes Technology Corporation
+  "^anlogic,.*":
+    description: Shanghai Anlogic Infotech Co., Ltd.
   "^anvo,.*":
     description: Anvo-Systems Dresden GmbH
   "^aoly,.*":
@@ -968,6 +970,8 @@ patternProperties:
     description: MikroElektronika d.o.o.
   "^mikrotik,.*":
     description: MikroTik
+  "^milianke,.*":
+    description: Changzhou Milianke Electronic Technology Co., Ltd
   "^milkv,.*":
     description: MilkV Technology Co., Ltd
   "^miniand,.*":
@@ -1081,6 +1085,8 @@ patternProperties:
     description: Novatek
   "^novtech,.*":
     description: NovTech, Inc.
+  "^nuclei,.*":
+    description: Nuclei System Technology
   "^numonyx,.*":
     description: Numonyx (deprecated, use micron)
     deprecated: true

-- 
2.50.1

Re: [PATCH RFC 01/10] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei

[Krzysztof Kozlowski]

On Mon, Jul 21, 2025 at 11:46:07PM +0800, Junhui Liu wrote:
> Add vendor prefixes for "anlogic", "milianke" and "nuclei". These are
> required for describing the Milianke MLKPAI-FS01 board with DR1V90 SoC
> from Anlogic, which uses a processor core designed by Nuclei.
> 
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

<form letter>
This is an automated instruction, just in case, because many review
tags are being ignored. If you know the process, just skip it entirely
(please do not feel offended by me posting it here - no bad intentions
intended, no patronizing, I just want to avoid wasted efforts). If you
do not know the process, here is a short explanation:

Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions of patchset, under or above your Signed-off-by tag, unless
patch changed significantly (e.g. new properties added to the DT
bindings). Tag is "received", when provided in a message replied to you
on the mailing list. Tools like b4 can help here ('b4 trailers -u ...').
However, there's no need to repost patches *only* to add the tags. The
upstream maintainer will do that for tags received on the version they
apply.

https://elixir.bootlin.com/linux/v6.15/source/Documentation/process/submitting-patches.rst#L591
</form letter>

Best regards,
Krzysztof

[PATCH RFC 02/10] dt-bindings: riscv: Add Nuclei UX900 compatibles

[Junhui Liu]

The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC.
It features a 64-bit architecture and dual-issue, 9-stage pipeline, with
lots of optional extensions including V, K, Zc, and more.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 2c72f148a74b019e46ad5917a0b75d45777c385e..f198d8b1fa328f538b4a2983ca795340337fbd2b 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
               - amd,mbv32
               - andestech,ax45mp
               - canaan,k210
+              - nuclei,ux900
               - sifive,bullet0
               - sifive,e5
               - sifive,e7

-- 
2.50.1

[PATCH RFC 03/10] dt-bindings: riscv: Add Anlogic DR1V90

[Junhui Liu]

Add Anlogic DR1V90 FPSoC, which is used by the Milianke MLKPAI-FS01
board.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 .../devicetree/bindings/riscv/anlogic.yaml         | 27 ++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/anlogic.yaml b/Documentation/devicetree/bindings/riscv/anlogic.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..91b1526c99aa3ca9cc7b0e7978861408bd017049
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/anlogic.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/anlogic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Anlogic SoC-based boards
+
+maintainers:
+  - Junhui Liu <junhui.liu@pigmoral.tech>
+
+description:
+  Anlogic SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milianke,mlkpai-fs01
+          - const: anlogic,dr1v90
+
+additionalProperties: true
+
+...

-- 
2.50.1

Re: [PATCH RFC 03/10] dt-bindings: riscv: Add Anlogic DR1V90

[Krzysztof Kozlowski]

On Mon, Jul 21, 2025 at 11:46:09PM +0800, Junhui Liu wrote:
> Add Anlogic DR1V90 FPSoC, which is used by the Milianke MLKPAI-FS01
> board.

Here you describe the hardware with more details.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH RFC 04/10] dt-bindings: timer: Add Anlogic DR1V90 CLINT

[Junhui Liu]

Add CLINT support for Anlogic DR1V90.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index d85a1a088b35dabc0aa202475b926302705c4cf1..16b8c0bdce82a55765046cfdc8d1f85a8dfb3912 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -29,6 +29,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - anlogic,dr1v90-clint    # Anlogic DR1V90
               - canaan,k210-clint       # Canaan Kendryte K210
               - eswin,eic7700-clint     # ESWIN EIC7700
               - sifive,fu540-c000-clint # SiFive FU540

-- 
2.50.1

Re: [PATCH RFC 04/10] dt-bindings: timer: Add Anlogic DR1V90 CLINT

[Rob Herring (Arm)]

On Mon, 21 Jul 2025 23:46:10 +0800, Junhui Liu wrote:
> Add CLINT support for Anlogic DR1V90.
> 
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH RFC 05/10] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC

[Junhui Liu]

Add PLIC support for Anlogic DR1V90.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml      | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index ffc4768bad065276378d23d53d6e81efad0a6b66..cc6de8bb89937859e4405aac5d931b8586ac2ddd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -57,6 +57,7 @@ properties:
           - const: andestech,nceplic100
       - items:
           - enum:
+              - anlogic,dr1v90-plic
               - canaan,k210-plic
               - sifive,fu540-c000-plic
               - spacemit,k1-plic

-- 
2.50.1

[PATCH RFC 06/10] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart

[Junhui Liu]

The Anlogic DR1V90 SoC integrates a UART controller compatible with
snps,dw-apb-uart, operating at a 50 MHz clock.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 8f1b7f704c5bc7cb9552b7d4825d96199cbc6c4f..ed00eefe17aa11200e0a10637d4cc10b68948699 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -51,6 +51,7 @@ properties:
           - const: renesas,rzn1-uart
       - items:
           - enum:
+              - anlogic,dr1v90-uart
               - brcm,bcm11351-dw-apb-uart
               - brcm,bcm21664-dw-apb-uart
               - rockchip,px30-uart

-- 
2.50.1

Re: [PATCH RFC 06/10] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart

[Rob Herring (Arm)]

On Mon, 21 Jul 2025 23:46:12 +0800, Junhui Liu wrote:
> The Anlogic DR1V90 SoC integrates a UART controller compatible with
> snps,dw-apb-uart, operating at a 50 MHz clock.
> 
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
>  Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH RFC 07/10] riscv: Add Anlogic SoC famly Kconfig support

[Junhui Liu]

The first SoC in the Anlogic series is DR1V90, which contains a RISC-V
core from Nuclei.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index a9c3d2f6debca1469f4a912b3414711eb709baab..de163cdddcda1c08e7c9e98716eaf043d4c4555a 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,10 @@
 menu "SoC selection"
 
+config ARCH_ANLOGIC
+	bool "Anlogic SoCs"
+	help
+		This enables support for Anlogic SoC platform hardware.
+
 config ARCH_MICROCHIP_POLARFIRE
 	def_bool ARCH_MICROCHIP
 

-- 
2.50.1

Re: [PATCH RFC 07/10] riscv: Add Anlogic SoC famly Kconfig support

[Krzysztof Kozlowski]

On Mon, Jul 21, 2025 at 11:46:13PM +0800, Junhui Liu wrote:
> The first SoC in the Anlogic series is DR1V90, which contains a RISC-V
> core from Nuclei.
> 
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
>  arch/riscv/Kconfig.socs | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index a9c3d2f6debca1469f4a912b3414711eb709baab..de163cdddcda1c08e7c9e98716eaf043d4c4555a 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -1,5 +1,10 @@
>  menu "SoC selection"
>  
> +config ARCH_ANLOGIC
> +	bool "Anlogic SoCs"
> +	help
> +		This enables support for Anlogic SoC platform hardware.

Wrong indentation. See everything else in this file or just read coding
style.

Best regards,
Krzysztof

Re: [PATCH RFC 07/10] riscv: Add Anlogic SoC famly Kconfig support

[Junhui Liu]

On 22/07/2025 09:29, Krzysztof Kozlowski wrote:
> On Mon, Jul 21, 2025 at 11:46:13PM +0800, Junhui Liu wrote:
>> The first SoC in the Anlogic series is DR1V90, which contains a RISC-V
>> core from Nuclei.
>> 
>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>> ---
>>  arch/riscv/Kconfig.socs | 5 +++++
>>  1 file changed, 5 insertions(+)
>> 
>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>> index a9c3d2f6debca1469f4a912b3414711eb709baab..de163cdddcda1c08e7c9e98716eaf043d4c4555a 100644
>> --- a/arch/riscv/Kconfig.socs
>> +++ b/arch/riscv/Kconfig.socs
>> @@ -1,5 +1,10 @@
>>  menu "SoC selection"
>>  
>> +config ARCH_ANLOGIC
>> +	bool "Anlogic SoCs"
>> +	help
>> +		This enables support for Anlogic SoC platform hardware.
> 
> Wrong indentation. See everything else in this file or just read coding
> style.

Thanks for pointing this out. I overlooked it and will fix it in the
next version.

> 
> Best regards,
> Krzysztof

-- 
Best regards,
Junhui Liu

[PATCH RFC 08/10] riscv: dts: Add initial Anlogic DR1V90 SoC device tree

[Junhui Liu]

DR1V90 is a FPSoC from Anlogic, which features a RISC-V core as the PS
part and 94,464 LUTs for the PL part.

The PS part integrates a Nuclei UX900 RISC-V core with 32KB L1 icache
and 32KB L1 dcache. It also provides two "snps,dw-apb-uart" compatible
UART controllers.

Currently, a "no4lvl" bootarg is required to force the kernel to use
3-level paging for successful boot. The DR1V90 hangs if SATP is set to
4/5-level paging modes during early boot, as detected in
set_satp_mode().

Some basic information of the processor can be obtained by running a
simple application from nuclei-sdk [1]:

-----Nuclei RISC-V CPU Configuration Information-----
         MARCHID: 0xc900
          MIMPID: 0x20300
             ISA: RV64 A B C D F I M P S U
            MCFG: TEE ECC ECLIC PLIC PPI ILM DLM ICACHE DCACHE IREGION No-Safety-Mechanism DLEN=VLEN/2
             ILM: 256 KB has-ecc
             DLM: 256 KB has-ecc
          ICACHE: 32 KB(set=256,way=2,lsize=64,ecc=1)
          DCACHE: 32 KB(set=256,way=2,lsize=64,ecc=1)
             TLB: MainTLB(set=32,way=2,entry=1,ecc=1) ITLB(entry=8) DTLB(entry=8)
         IREGION: 0x68000000 128 MB
                  Unit        Size        Address
                  INFO        64KB        0x68000000
                  DEBUG       64KB        0x68010000
                  ECLIC       64KB        0x68020000
                  TIMER       64KB        0x68030000
                  PLIC        64MB        0x6c000000
     INFO-Detail:
                  mpasize : 0
             PPI: 0xf8000000 128 MB
-----End of Nuclei CPU INFO-----

Link: https://github.com/Nuclei-Software/nuclei-sdk/blob/master/application/baremetal/cpuinfo/main.c [1]
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 86 +++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..e1e3f6b72e56abce5a35e6d7571c91a64b0fecff
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+/dts-v1/;
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Anlogic DR1V90";
+	compatible = "anlogic,dr1v90";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <800000000>;
+
+		cpu@0 {
+			compatible = "nuclei,ux900", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
+					       "zbkc", "zbs", "zicntr", "zicsr", "zifencei",
+					       "zihintpause", "zihpm";
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <256>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <256>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clint: timer@68030000 {
+			compatible = "anlogic,dr1v90-clint", "sifive,clint0";
+			reg = <0x0 0x68030000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+		};
+
+		plic: interrupt-controller@6c000000 {
+			compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0x6c000000 0x0 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			riscv,ndev = <150>;
+		};
+
+		uart0: serial@f8400000 {
+			compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
+			reg = <0x0 0xf8400000 0x0 0x1000>;
+			interrupts = <71>;
+			clock-frequency = <50000000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@f8401000 {
+			compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
+			reg = <0x0 0xf8401000 0x0 0x1000>;
+			interrupts = <72>;
+			clock-frequency = <50000000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+	};
+};

-- 
2.50.1

Re: [PATCH RFC 08/10] riscv: dts: Add initial Anlogic DR1V90 SoC device tree

[Conor Dooley]

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On Mon, Jul 21, 2025 at 11:46:14PM +0800, Junhui Liu wrote:
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <800000000>;
> +
> +		cpu@0 {
> +			compatible = "nuclei,ux900", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			riscv,isa = "rv64imafdc";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
> +					       "zbkc", "zbs", "zicntr", "zicsr", "zifencei",
> +					       "zihintpause", "zihpm";

Why do riscv,isa and riscv,isa-extensions differ?
If riscv,isa is not even accurate, why not just remove it entirely?

> +			i-cache-block-size = <64>;
> +			i-cache-size = <32768>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <32768>;
> +			d-cache-sets = <256>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +	};

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Re: [PATCH RFC 08/10] riscv: dts: Add initial Anlogic DR1V90 SoC device tree

[Junhui Liu]

On 22/07/2025 16:21, Conor Dooley wrote:
> On Mon, Jul 21, 2025 at 11:46:14PM +0800, Junhui Liu wrote:
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		timebase-frequency = <800000000>;
>> +
>> +		cpu@0 {
>> +			compatible = "nuclei,ux900", "riscv";
>> +			device_type = "cpu";
>> +			reg = <0>;
>> +			riscv,isa = "rv64imafdc";
>> +			riscv,isa-base = "rv64i";
>> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
>> +					       "zbkc", "zbs", "zicntr", "zicsr", "zifencei",
>> +					       "zihintpause", "zihpm";
> 
> Why do riscv,isa and riscv,isa-extensions differ?
> If riscv,isa is not even accurate, why not just remove it entirely?

You're right, they should be the same. I will remove "riscv,isa" and
keep only "riscv,isa-base" and "riscv,isa-extensions".
Thanks for pointing it out, I will fix this in the next version.

> 
>> +			i-cache-block-size = <64>;
>> +			i-cache-size = <32768>;
>> +			i-cache-sets = <256>;
>> +			d-cache-block-size = <64>;
>> +			d-cache-size = <32768>;
>> +			d-cache-sets = <256>;
>> +			mmu-type = "riscv,sv39";
>> +
>> +			cpu0_intc: interrupt-controller {
>> +				compatible = "riscv,cpu-intc";
>> +				interrupt-controller;
>> +				#interrupt-cells = <1>;
>> +			};
>> +		};
>> +	};

-- 
Best regards,
Junhui Liu

[PATCH RFC 09/10] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board

[Junhui Liu]

Add support for the Milianke MLKPAI FS01 board based on the Anlogic
DR1V90 SoC. The board features 512MB of onboard memory, with the region
after 0x1fe00000 reserved for OpenSBI.

Currently, the board can boot to a console via UART1, which is connected
to the onboard serial chip and routed to the Type-C interface.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/anlogic/Makefile               |  2 ++
 arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 ++++++++++++++++++++++
 3 files changed, 31 insertions(+)

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 64a898da9aee33f5c10cd332ad59b945615816bf..d423b825160c7cc0248b258126867531b9687e23 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += allwinner
+subdir-y += anlogic
 subdir-y += canaan
 subdir-y += microchip
 subdir-y += renesas
diff --git a/arch/riscv/boot/dts/anlogic/Makefile b/arch/riscv/boot/dts/anlogic/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..87f3b2f418cfa32012df5ae82d17262a9610f90c
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ANLOGIC) += dr1v90-mlkpai-fs01.dtb
diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts
new file mode 100644
index 0000000000000000000000000000000000000000..6a9dca4b6e39261bdef63df5f158c89a323f1732
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include "dr1v90.dtsi"
+
+/ {
+	model = "Milianke MLKPAI-FS01";
+	compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x1fe00000>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+};

-- 
2.50.1

Re: [PATCH RFC 09/10] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board

[Krzysztof Kozlowski]

On Mon, Jul 21, 2025 at 11:46:15PM +0800, Junhui Liu wrote:
> Add support for the Milianke MLKPAI FS01 board based on the Anlogic
> DR1V90 SoC. The board features 512MB of onboard memory, with the region
> after 0x1fe00000 reserved for OpenSBI.
> 
> Currently, the board can boot to a console via UART1, which is connected
> to the onboard serial chip and routed to the Type-C interface.
> 
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
>  arch/riscv/boot/dts/Makefile                       |  1 +
>  arch/riscv/boot/dts/anlogic/Makefile               |  2 ++
>  arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 ++++++++++++++++++++++
>  3 files changed, 31 insertions(+)

You need maintainers entry for your entire sub-arch. Otherwise why would
we want unmaintained code?

Best regards,
Krzysztof

Re: [PATCH RFC 09/10] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board

[Junhui Liu]

On 22/07/2025 09:31, Krzysztof Kozlowski wrote:
> On Mon, Jul 21, 2025 at 11:46:15PM +0800, Junhui Liu wrote:
>> Add support for the Milianke MLKPAI FS01 board based on the Anlogic
>> DR1V90 SoC. The board features 512MB of onboard memory, with the region
>> after 0x1fe00000 reserved for OpenSBI.
>> 
>> Currently, the board can boot to a console via UART1, which is connected
>> to the onboard serial chip and routed to the Type-C interface.
>> 
>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>> ---
>>  arch/riscv/boot/dts/Makefile                       |  1 +
>>  arch/riscv/boot/dts/anlogic/Makefile               |  2 ++
>>  arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 ++++++++++++++++++++++
>>  3 files changed, 31 insertions(+)
> 
> You need maintainers entry for your entire sub-arch. Otherwise why would
> we want unmaintained code?

Thanks for your reminder, I will add the relevant information to the
MAINTAINERS file.

> 
> Best regards,
> Krzysztof

-- 
Best regards,
Junhui Liu

[PATCH RFC 10/10] riscv: defconfig: Enable Anlogic SoC

[Junhui Liu]

Enable Anlogic SoC config in defconfig to allow the default upstream
kernel booting on Milianke MLKPAI-FS01 board.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index fe8bd8afb4183ce871020fb2992a21a13bccbc87..9b096dde47a3a4328cd4c9abae6730780ec8fba2 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -22,6 +22,7 @@ CONFIG_USER_NS=y
 CONFIG_CHECKPOINT_RESTORE=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_PROFILING=y
+CONFIG_ARCH_ANLOGIC=y
 CONFIG_ARCH_MICROCHIP=y
 CONFIG_ARCH_SIFIVE=y
 CONFIG_ARCH_SOPHGO=y

-- 
2.50.1