From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD5AF2C3254; Tue, 22 Jul 2025 07:19:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753168776; cv=none; b=ZnmofboPlnswhtxc4mSlK4wXELcCkbVe94/HnyR/Fu5sk0bGuUPtuUC2rNlc02nW+76DU//VIeRZBAhRrF6DPWWuXS8GNgs2Qnwc78WMAV37BFWyhkVtQ+R7pBjx1VRzE2NMg6LU4cJHeD+j+AS3SKb9rX//rgKbGdYSH4CzT3Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753168776; c=relaxed/simple; bh=6AgzjhBZxA3wEqcXfXHf90mqgnB60GOi2YIsHje5XqM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=RxhgXS/r524nnMM9wstATg9xORlPzWaT1sW+gSyA3lOlXBar2jRWGCTbqHycs3WBTrWbM9vp6YX0QyaO7C1M62A02g6nyclqrZHTichzc/I+IHnT9/lQVSpHjaOACnhvV9IMPymzGbU8k7JUUqffA+u937b2PHvcx7L0YO3SW2o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WQRGtc2A; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WQRGtc2A" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8300C4CEEB; Tue, 22 Jul 2025 07:19:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753168776; bh=6AgzjhBZxA3wEqcXfXHf90mqgnB60GOi2YIsHje5XqM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=WQRGtc2A+jcXZ+jiKUu3KUdQL2TgUEQKNuEmGtlIGvKGw1rmPkiNMcCTvewcahhHN tJk2rRkVl+Zz1j4PdYX2PAvkl5oysQ/nkCKOXxFU1pom7zUp+zCa50T9aycvTO6R+z fDzsYdpwBB70PQaqXsFoWjDqppVQNDFPeb6Uvop3PhG5cB49SJEF/1ibkCXCQ4ryw/ EIVEQQXcvV4XYtvmX8Chxhy/g3eZoB36XPzLKt2+DLd+eYr3I1O35dyACfZhcPvf8m AVatrVdWRZXoLef4eIcCcUFKGpO4qpNl37IeU6iZHdkiljZ6InRW9zvRyJUt7yei0t aaS/gaELh+S9w== Date: Tue, 22 Jul 2025 09:19:33 +0200 From: Krzysztof Kozlowski To: Otto =?utf-8?Q?Pfl=C3=BCger?= Cc: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Orson Zhai , Baolin Wang , Chunyan Zhang , Kevin Tang , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 01/12] dt-bindings: display: sprd: adapt for UMS9230 support Message-ID: <20250722-imported-origami-cat-dbfaad@kuoka> References: <20250719-ums9230-drm-v1-0-e4344a05eb3d@abscue.de> <20250719-ums9230-drm-v1-1-e4344a05eb3d@abscue.de> <9966b9e4-399b-4446-81e4-15daf9acbff7@kernel.org> <40fd4502-71d5-435e-83f2-2df933c0467b@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: On Sun, Jul 20, 2025 at 07:35:24PM +0200, Otto Pfl=C3=BCger wrote: > On Sun, Jul 20, 2025 at 05:38:02PM +0200, Krzysztof Kozlowski wrote: > > >=20 > > > The clocks should be the same on sharkl3 (sc9863a) and ums9230, but > > > the existing bindings don't really make sense here or are incomplete. > > > AFAIK there is no SoC in which this display controller is directly > > > connected to the PLL as shown in the example. The DSI controller is > >=20 > > This is not the PLL. Gate either. You are looking from wrong side - how > > clock is generated. > >=20 > > You describe here CLOCK INPUT. > >=20 > > > connected to a clock gate. The DPU actually does have two clocks, both > > > of which are clock muxes that allow selecting different frequencies a= nd > > > one of which is behind a clock gate. I can add the second clock for t= he > > > DPU if needed. > > >=20 > > > Since nothing seems to be using these bindings at the moment, would it > > > be okay to drop the old clock names that refer to specific frequencie= s? > >=20 > > It is still completely irrelevant whether these are muxes. Dropping > > existing properties is ABI change, but anyway first figure out what is > > here really. >=20 > I was trying to point out that the existing clock names are incorrect > because they refer to a specific source that is not necessarily used > for these clocks, instead of giving a name for the clock input. OK, if the old name refers to the same clock input as in your new device, you can deprecate old case in the binding. >=20 > For the DPU, would "core" and "dpi" be more appropriate as clock names? > DPI refers to the interface used internally between the DPU and the DSI > controller. Sounds fine. >=20 > For the DSI controller, it seems that the clock is actually an APB bus > clock needed for accessing the control registers. Again, it is not > required to be connected to a 96MHz clock source as the name used in the > binding suggests. Would something like "apb_clk" or "pclk" be more > descriptive? Yeah, both are correct. I think pclk is preferred. Best regards, Krzysztof