* [PATCH v3 0/4] i3c: add support for the Renesas controller
@ 2025-07-22 15:34 Wolfram Sang
2025-07-22 15:34 ` [PATCH v3 3/4] dt-bindings: i3c: Add Renesas I3C controller Wolfram Sang
0 siblings, 1 reply; 3+ messages in thread
From: Wolfram Sang @ 2025-07-22 15:34 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Wolfram Sang, Alexandre Belloni, Conor Dooley, devicetree,
Frank Li, Geert Uytterhoeven, Gustavo A. R. Silva, Kees Cook,
Krzysztof Kozlowski, linux-hardening, linux-i3c, Magnus Damm,
Philipp Zabel, Rob Herring, Tommaso Merciai
Conceptual change since v2:
* improve and add more parameters from the spec to master.h
(new patches 1+2)
Detailed changes since v2 are described in the individual patches. A
branch with enablement patches for RZ/G3S+G3E can be found here:
git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git renesas/g3s/i3c
Old coverletter:
Here is a basic driver for the I3C IP found in various Renesas SoCs like
RZ/G3S and G3E. Missing features to be added incrementally are IBI,
HotJoin and maybe target support. Other than that, this driver has been
tested with I3C pure busses (2 targets) and mixed busses (2 I3C +
various I2C targets). DAA and reading/writing to the temperature sensors
worked reliably at different speeds. Scoping the bus, the output from
the protocol analyzer seems reasonable, too. It was created by merging
two versions of it from two different BSPs. Then, improved according to
code analyzers, cleaned up with regard to coding style, and then
refactored to hopefully match I3C subsystem standards.
Looking forward to comments,
Wolfram
Tommaso Merciai (1):
dt-bindings: i3c: Add Renesas I3C controller
Wolfram Sang (3):
i3c: Harmonize defines representing specification parameters
i3c: Add more parameters for controllers to the header
i3c: master: Add basic driver for the Renesas I3C controller
.../devicetree/bindings/i3c/renesas,i3c.yaml | 179 +++
MAINTAINERS | 7 +
drivers/i3c/master.c | 12 +-
drivers/i3c/master/Kconfig | 10 +
drivers/i3c/master/Makefile | 1 +
drivers/i3c/master/dw-i3c-master.c | 4 +-
drivers/i3c/master/renesas-i3c.c | 1404 +++++++++++++++++
include/linux/i3c/master.h | 16 +-
8 files changed, 1621 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
create mode 100644 drivers/i3c/master/renesas-i3c.c
--
2.47.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v3 3/4] dt-bindings: i3c: Add Renesas I3C controller
2025-07-22 15:34 [PATCH v3 0/4] i3c: add support for the Renesas controller Wolfram Sang
@ 2025-07-22 15:34 ` Wolfram Sang
2025-07-22 18:13 ` Frank Li
0 siblings, 1 reply; 3+ messages in thread
From: Wolfram Sang @ 2025-07-22 15:34 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Tommaso Merciai, Wolfram Sang, Rob Herring (Arm),
Alexandre Belloni, Frank Li, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, linux-i3c, devicetree
From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Add Renesas I3C controller which is available in R9A08G045 (RZ/G3S) and
R9A09G047 (RZ/G3E) SoCs.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
Change since v2:
* rev-tag added, thanks Rob!
.../devicetree/bindings/i3c/renesas,i3c.yaml | 179 ++++++++++++++++++
1 file changed, 179 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
diff --git a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
new file mode 100644
index 000000000000..fe2e9633c46f
--- /dev/null
+++ b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3S and RZ/G3E I3C Bus Interface
+
+maintainers:
+ - Wolfram Sang <wsa+renesas@sang-engineering.com>
+ - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a08g045-i3c # RZ/G3S
+ - renesas,r9a09g047-i3c # RZ/G3E
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Non-recoverable internal error interrupt
+ - description: Normal transfer error interrupt
+ - description: Normal transfer abort interrupt
+ - description: Normal response status buffer full interrupt
+ - description: Normal command buffer empty interrupt
+ - description: Normal IBI status buffer full interrupt
+ - description: Normal Rx data buffer full interrupt
+ - description: Normal Tx data buffer empty interrupt
+ - description: Normal receive status buffer full interrupt
+ - description: START condition detection interrupt
+ - description: STOP condition detection interrupt
+ - description: Transmit end interrupt
+ - description: NACK detection interrupt
+ - description: Arbitration lost interrupt
+ - description: Timeout detection interrupt
+ - description: Wake-up condition detection interrupt
+ - description: HDR Exit Pattern detection interrupt
+ minItems: 16
+
+ interrupt-names:
+ items:
+ - const: ierr
+ - const: terr
+ - const: abort
+ - const: resp
+ - const: cmd
+ - const: ibi
+ - const: rx
+ - const: tx
+ - const: rcv
+ - const: st
+ - const: sp
+ - const: tend
+ - const: nack
+ - const: al
+ - const: tmo
+ - const: wu
+ - const: exit
+ minItems: 16
+
+ clocks:
+ items:
+ - description: APB bus clock
+ - description: transfer clock
+ - description: SFRs clock
+ minItems: 2
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: tclk
+ - const: pclkrw
+ minItems: 2
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: Reset signal
+ - description: APB interface reset signal/SCAN reset signal
+
+ reset-names:
+ items:
+ - const: presetn
+ - const: tresetn
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clock-names
+ - clocks
+ - power-domains
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: i3c.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a08g045-i3c
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+ interrupts:
+ minItems: 17
+ interrupt-names:
+ minItems: 17
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g047-i3c
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ clock-names:
+ minItems: 3
+ interrupts:
+ maxItems: 16
+ interrupt-names:
+ maxItems: 16
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a08g045-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ i3c@1005b000 {
+ compatible = "renesas,r9a08g045-i3c";
+ reg = <0x1005b000 0x1000>;
+ clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
+ <&cpg CPG_MOD R9A08G045_I3C_TCLK>;
+ clock-names = "pclk", "tclk";
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ierr", "terr", "abort", "resp",
+ "cmd", "ibi", "rx", "tx", "rcv",
+ "st", "sp", "tend", "nack",
+ "al", "tmo", "wu", "exit";
+ resets = <&cpg R9A08G045_I3C_PRESETN>,
+ <&cpg R9A08G045_I3C_TRESETN>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ };
+...
--
2.47.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v3 3/4] dt-bindings: i3c: Add Renesas I3C controller
2025-07-22 15:34 ` [PATCH v3 3/4] dt-bindings: i3c: Add Renesas I3C controller Wolfram Sang
@ 2025-07-22 18:13 ` Frank Li
0 siblings, 0 replies; 3+ messages in thread
From: Frank Li @ 2025-07-22 18:13 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-renesas-soc, Tommaso Merciai, Rob Herring (Arm),
Alexandre Belloni, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, linux-i3c, devicetree
On Tue, Jul 22, 2025 at 05:34:41PM +0200, Wolfram Sang wrote:
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>
> Add Renesas I3C controller which is available in R9A08G045 (RZ/G3S) and
> R9A09G047 (RZ/G3E) SoCs.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> Change since v2:
> * rev-tag added, thanks Rob!
>
> .../devicetree/bindings/i3c/renesas,i3c.yaml | 179 ++++++++++++++++++
> 1 file changed, 179 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
>
> diff --git a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
> new file mode 100644
> index 000000000000..fe2e9633c46f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
> @@ -0,0 +1,179 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G3S and RZ/G3E I3C Bus Interface
> +
> +maintainers:
> + - Wolfram Sang <wsa+renesas@sang-engineering.com>
> + - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a08g045-i3c # RZ/G3S
> + - renesas,r9a09g047-i3c # RZ/G3E
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: Non-recoverable internal error interrupt
> + - description: Normal transfer error interrupt
> + - description: Normal transfer abort interrupt
> + - description: Normal response status buffer full interrupt
> + - description: Normal command buffer empty interrupt
> + - description: Normal IBI status buffer full interrupt
> + - description: Normal Rx data buffer full interrupt
> + - description: Normal Tx data buffer empty interrupt
> + - description: Normal receive status buffer full interrupt
> + - description: START condition detection interrupt
> + - description: STOP condition detection interrupt
> + - description: Transmit end interrupt
> + - description: NACK detection interrupt
> + - description: Arbitration lost interrupt
> + - description: Timeout detection interrupt
> + - description: Wake-up condition detection interrupt
> + - description: HDR Exit Pattern detection interrupt
> + minItems: 16
> +
> + interrupt-names:
> + items:
> + - const: ierr
> + - const: terr
> + - const: abort
> + - const: resp
> + - const: cmd
> + - const: ibi
> + - const: rx
> + - const: tx
> + - const: rcv
> + - const: st
> + - const: sp
> + - const: tend
> + - const: nack
> + - const: al
> + - const: tmo
> + - const: wu
> + - const: exit
> + minItems: 16
> +
> + clocks:
> + items:
> + - description: APB bus clock
> + - description: transfer clock
> + - description: SFRs clock
> + minItems: 2
> +
> + clock-names:
> + items:
> + - const: pclk
> + - const: tclk
> + - const: pclkrw
> + minItems: 2
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + items:
> + - description: Reset signal
> + - description: APB interface reset signal/SCAN reset signal
> +
> + reset-names:
> + items:
> + - const: presetn
> + - const: tresetn
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clock-names
> + - clocks
> + - power-domains
> + - resets
> + - reset-names
> +
> +allOf:
> + - $ref: i3c.yaml#
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a08g045-i3c
> + then:
> + properties:
> + clocks:
> + maxItems: 2
> + clock-names:
> + maxItems: 2
> + interrupts:
> + minItems: 17
> + interrupt-names:
> + minItems: 17
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g047-i3c
> + then:
> + properties:
> + clocks:
> + minItems: 3
> + clock-names:
> + minItems: 3
> + interrupts:
> + maxItems: 16
> + interrupt-names:
> + maxItems: 16
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r9a08g045-cpg.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + i3c@1005b000 {
> + compatible = "renesas,r9a08g045-i3c";
> + reg = <0x1005b000 0x1000>;
> + clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
> + <&cpg CPG_MOD R9A08G045_I3C_TCLK>;
> + clock-names = "pclk", "tclk";
> + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "ierr", "terr", "abort", "resp",
> + "cmd", "ibi", "rx", "tx", "rcv",
> + "st", "sp", "tend", "nack",
> + "al", "tmo", "wu", "exit";
> + resets = <&cpg R9A08G045_I3C_PRESETN>,
> + <&cpg R9A08G045_I3C_TRESETN>;
> + reset-names = "presetn", "tresetn";
> + power-domains = <&cpg>;
> + #address-cells = <3>;
> + #size-cells = <0>;
> + };
> +...
> --
> 2.47.2
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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