* [PATCH v6 01/10] dt-bindings: vendor-prefixes: Add Axiado Corporation
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-22 20:15 ` [PATCH v6 02/10] dt-bindings: arm: axiado: add AX3000 EVK compatible strings Harshit Shah
` (9 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah
Link: https://axiado.com
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 5d2a7a8d3ac6c666c8b557c2ef385918e5e97bf9..5ada930c79e3b32ff1bf194ee66bb4bdb08d539e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -200,6 +200,8 @@ patternProperties:
description: Shanghai Awinic Technology Co., Ltd.
"^axentia,.*":
description: Axentia Technologies AB
+ "^axiado,.*":
+ description: Axiado Corporation
"^axis,.*":
description: Axis Communications AB
"^azoteq,.*":
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 02/10] dt-bindings: arm: axiado: add AX3000 EVK compatible strings
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
2025-07-22 20:15 ` [PATCH v6 01/10] dt-bindings: vendor-prefixes: Add Axiado Corporation Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-22 20:15 ` [PATCH v6 03/10] dt-bindings: gpio: cdns: convert to YAML Harshit Shah
` (8 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah, Krzysztof Kozlowski
Add device tree binding schema for Axiado platforms, specifically the
AX3000 SoC and its associated evaluation board. This binding will be
used for the board-level DTS files that support the AX3000 platforms.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
Documentation/devicetree/bindings/arm/axiado.yaml | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/axiado.yaml b/Documentation/devicetree/bindings/arm/axiado.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..bfabe7b32e65fb06d1f4faecfad032219f95dfca
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/axiado.yaml
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/axiado.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axiado Platforms
+
+maintainers:
+ - Harshit Shah <hshah@axiado.com>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: AX3000 based boards
+ items:
+ - enum:
+ - axiado,ax3000-evk # Axiado AX3000 Evaluation Board
+ - const: axiado,ax3000 # Axiado AX3000 SoC
+
+additionalProperties: true
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 03/10] dt-bindings: gpio: cdns: convert to YAML
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
2025-07-22 20:15 ` [PATCH v6 01/10] dt-bindings: vendor-prefixes: Add Axiado Corporation Harshit Shah
2025-07-22 20:15 ` [PATCH v6 02/10] dt-bindings: arm: axiado: add AX3000 EVK compatible strings Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-22 20:15 ` [PATCH v6 04/10] dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant Harshit Shah
` (7 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah, Krzysztof Kozlowski
Convert Cadence family GPIO controller bindings to DT schema.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
.../devicetree/bindings/gpio/cdns,gpio.txt | 43 ------------
.../devicetree/bindings/gpio/cdns,gpio.yaml | 79 ++++++++++++++++++++++
2 files changed, 79 insertions(+), 43 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.txt b/Documentation/devicetree/bindings/gpio/cdns,gpio.txt
deleted file mode 100644
index 706ef00f5c64951bb29c79a5541db4397e8b2733..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/gpio/cdns,gpio.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-Cadence GPIO controller bindings
-
-Required properties:
-- compatible: should be "cdns,gpio-r1p02".
-- reg: the register base address and size.
-- #gpio-cells: should be 2.
- * first cell is the GPIO number.
- * second cell specifies the GPIO flags, as defined in
- <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
- and GPIO_ACTIVE_LOW flags are supported.
-- gpio-controller: marks the device as a GPIO controller.
-- clocks: should contain one entry referencing the peripheral clock driving
- the GPIO controller.
-
-Optional properties:
-- ngpios: integer number of gpio lines supported by this controller, up to 32.
-- interrupts: interrupt specifier for the controllers interrupt.
-- interrupt-controller: marks the device as an interrupt controller. When
- defined, interrupts, interrupt-parent and #interrupt-cells
- are required.
-- interrupt-cells: should be 2.
- * first cell is the GPIO number you want to use as an IRQ source.
- * second cell specifies the IRQ type, as defined in
- <dt-bindings/interrupt-controller/irq.h>.
- Currently only level sensitive IRQs are supported.
-
-
-Example:
- gpio0: gpio-controller@fd060000 {
- compatible = "cdns,gpio-r1p02";
- reg =<0xfd060000 0x1000>;
-
- clocks = <&gpio_clk>;
-
- interrupt-parent = <&gic>;
- interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..f1a64c17366500cb0e02a0ca90da691fd992fe7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/cdns,gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence GPIO Controller
+
+maintainers:
+ - Jan Kotas <jank@cadence.com>
+
+properties:
+ compatible:
+ const: cdns,gpio-r1p02
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ ngpios:
+ minimum: 1
+ maximum: 32
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ - First cell is the GPIO line number.
+ - Second cell is flags as defined in <dt-bindings/gpio/gpio.h>,
+ only GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW supported.
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+ description: |
+ - First cell is the GPIO line number used as IRQ.
+ - Second cell is the trigger type, as defined in
+ <dt-bindings/interrupt-controller/irq.h>.
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - gpio-controller
+ - "#gpio-cells"
+
+if:
+ required: [interrupt-controller]
+then:
+ required:
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ gpio0: gpio-controller@fd060000 {
+ compatible = "cdns,gpio-r1p02";
+ reg = <0xfd060000 0x1000>;
+ clocks = <&gpio_clk>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 04/10] dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
` (2 preceding siblings ...)
2025-07-22 20:15 ` [PATCH v6 03/10] dt-bindings: gpio: cdns: convert to YAML Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-22 20:15 ` [PATCH v6 05/10] dt-bindings: serial: cdns: add Axiado AX3000 UART controller Harshit Shah
` (6 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah, Krzysztof Kozlowski
Add binding for Axiado AX3000 GPIO controller. So far, no changes
are known, so it can fallback to default compatible.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
Documentation/devicetree/bindings/gpio/cdns,gpio.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
index f1a64c17366500cb0e02a0ca90da691fd992fe7d..a84d60b3945952a1991492064ae6494df91c966f 100644
--- a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
@@ -11,7 +11,12 @@ maintainers:
properties:
compatible:
- const: cdns,gpio-r1p02
+ oneOf:
+ - const: cdns,gpio-r1p02
+ - items:
+ - enum:
+ - axiado,ax3000-gpio
+ - const: cdns,gpio-r1p02
reg:
maxItems: 1
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 05/10] dt-bindings: serial: cdns: add Axiado AX3000 UART controller
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
` (3 preceding siblings ...)
2025-07-22 20:15 ` [PATCH v6 04/10] dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-22 20:15 ` [PATCH v6 06/10] dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller Harshit Shah
` (5 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah, Krzysztof Kozlowski
Add binding for AX3000 UART controller. So far, no changes known,
so it can fallback to default compatible.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
Documentation/devicetree/bindings/serial/cdns,uart.yaml | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
index d7f047b0bf24c444e2d81e0156fb01a89207ee2a..9d3e5c1d8502272f8b08f7d59f18d5e6be25d891 100644
--- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
@@ -16,9 +16,10 @@ properties:
items:
- const: xlnx,xuartps
- const: cdns,uart-r1p8
- - description: UART controller for Zynq Ultrascale+ MPSoC
- items:
- - const: xlnx,zynqmp-uart
+ - items:
+ - enum:
+ - axiado,ax3000-uart
+ - xlnx,zynqmp-uart
- const: cdns,uart-r1p12
reg:
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 06/10] dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
` (4 preceding siblings ...)
2025-07-22 20:15 ` [PATCH v6 05/10] dt-bindings: serial: cdns: add Axiado AX3000 UART controller Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-22 22:42 ` Alexandre Belloni
2025-07-22 20:15 ` [PATCH v6 07/10] arm64: add Axiado SoC family Harshit Shah
` (4 subsequent siblings)
10 siblings, 1 reply; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah, Krzysztof Kozlowski
Add binding for AX3000 I3C controller. So far, no changes known,
so it can fallback to default compatible.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
index cad6d53d0e2e35ddaaad35215ec93dd182f28319..6fa3078074d0298d9786a26d7f1f2dd2c15329a7 100644
--- a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
+++ b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
@@ -14,7 +14,12 @@ allOf:
properties:
compatible:
- const: cdns,i3c-master
+ oneOf:
+ - const: cdns,i3c-master
+ - items:
+ - enum:
+ - axiado,ax3000-i3c
+ - const: cdns,i3c-master
reg:
maxItems: 1
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 06/10] dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
2025-07-22 20:15 ` [PATCH v6 06/10] dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller Harshit Shah
@ 2025-07-22 22:42 ` Alexandre Belloni
0 siblings, 0 replies; 15+ messages in thread
From: Alexandre Belloni @ 2025-07-22 22:42 UTC (permalink / raw)
To: Harshit Shah
Cc: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Frank Li, Boris Brezillon, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Linus Walleij, Bartosz Golaszewski, Arnd Bergmann,
Catalin Marinas, Will Deacon, soc, devicetree, linux-kernel,
linux-arm-kernel, linux-gpio, Jan Kotas, linux-serial, linux-i3c,
Krzysztof Kozlowski
On 22/07/2025 13:15:34-0700, Harshit Shah wrote:
> Add binding for AX3000 I3C controller. So far, no changes known,
> so it can fallback to default compatible.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Harshit Shah <hshah@axiado.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
> index cad6d53d0e2e35ddaaad35215ec93dd182f28319..6fa3078074d0298d9786a26d7f1f2dd2c15329a7 100644
> --- a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
> @@ -14,7 +14,12 @@ allOf:
>
> properties:
> compatible:
> - const: cdns,i3c-master
> + oneOf:
> + - const: cdns,i3c-master
> + - items:
> + - enum:
> + - axiado,ax3000-i3c
> + - const: cdns,i3c-master
>
> reg:
> maxItems: 1
>
> --
> 2.25.1
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 07/10] arm64: add Axiado SoC family
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
` (5 preceding siblings ...)
2025-07-22 20:15 ` [PATCH v6 06/10] dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-22 20:15 ` [PATCH v6 08/10] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board Harshit Shah
` (3 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah, Krzysztof Kozlowski
Add ARCH_AXIADO for the support of the Axiado SoC for arm64 architecture.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
arch/arm64/Kconfig.platforms | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index a541bb029aa4e1bee095ab3f44e3a52294905616..e998e1aff0fec4aca5e3bf2d0410f2578e25cb1d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -40,6 +40,12 @@ config ARCH_APPLE
This enables support for Apple's in-house ARM SoC family, such
as the Apple M1.
+config ARCH_AXIADO
+ bool "Axiado SoC Family"
+ select GPIOLIB
+ help
+ This enables support for Axiado SoC family like AX3000
+
menuconfig ARCH_BCM
bool "Broadcom SoC Support"
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 08/10] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
` (6 preceding siblings ...)
2025-07-22 20:15 ` [PATCH v6 07/10] arm64: add Axiado SoC family Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-22 20:15 ` [PATCH v6 09/10] arm64: defconfig: enable the Axiado family Harshit Shah
` (2 subsequent siblings)
10 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah, Krzysztof Kozlowski
Add initial device tree support for the AX3000 SoC and its evaluation
platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
Secure Vault, AI Engine and Firewall.
It adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
controllers on the AX3000 evaluation board.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/axiado/Makefile | 2 +
arch/arm64/boot/dts/axiado/ax3000-evk.dts | 79 +++++
arch/arm64/boot/dts/axiado/ax3000.dtsi | 520 ++++++++++++++++++++++++++++++
4 files changed, 602 insertions(+)
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += amlogic
subdir-y += apm
subdir-y += apple
subdir-y += arm
+subdir-y += axiado
subdir-y += bitmain
subdir-y += blaize
subdir-y += broadcom
diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..6676ad07db6129f8b333b0feffee705d272517c2
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb
diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
new file mode 100644
index 0000000000000000000000000000000000000000..92101c5b534bfac8b463adaa1c4f0d4367d01e21
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ax3000.dtsi"
+
+/ {
+ model = "Axiado AX3000 EVK";
+ compatible = "axiado,ax3000-evk", "axiado,ax3000";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* Cortex-A53 will use following memory map */
+ reg = <0x00000000 0x3d000000 0x00000000 0x23000000>,
+ <0x00000004 0x00000000 0x00000000 0x80000000>;
+ };
+};
+
+/* GPIO bank 0 - 7 */
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&gpio6 {
+ status = "okay";
+};
+
+&gpio7 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..792f52e0c7dd42cbc54b0eb47e25b0fbf1a706b8
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
@@ -0,0 +1,520 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
+/ {
+ model = "Axiado AX3000";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-unified;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+ };
+
+ clocks {
+ clk_xin: clock-200000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "clk_xin";
+ };
+
+ refclk: clock-125000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic500>;
+
+ gic500: interrupt-controller@80300000 {
+ compatible = "arm,gic-v3";
+ reg = <0x00 0x80300000 0x00 0x10000>,
+ <0x00 0x80380000 0x00 0x80000>;
+ ranges;
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* GPIO Controller banks 0 - 7 */
+ gpio0: gpio-controller@80500000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x00 0x80500000 0x00 0x400>;
+ clocks = <&refclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@80580000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x00 0x80580000 0x00 0x400>;
+ clocks = <&refclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio-controller@80600000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x00 0x80600000 0x00 0x400>;
+ clocks = <&refclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio3: gpio-controller@80680000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x00 0x80680000 0x00 0x400>;
+ clocks = <&refclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio4: gpio-controller@80700000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x00 0x80700000 0x00 0x400>;
+ clocks = <&refclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio5: gpio-controller@80780000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x00 0x80780000 0x00 0x400>;
+ clocks = <&refclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio6: gpio-controller@80800000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x00 0x80800000 0x00 0x400>;
+ clocks = <&refclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio7: gpio-controller@80880000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x00 0x80880000 0x00 0x400>;
+ clocks = <&refclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ /* I3C Controller 0 - 16 */
+ i3c0: i3c@80500400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80500400 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c1: i3c@80500800 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80500800 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c2: i3c@80580400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80580400 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c3: i3c@80580800 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80580800 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c4: i3c@80600400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80600400 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c5: i3c@80600800 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80600800 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c6: i3c@80680400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80680400 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c7: i3c@80680800 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80680800 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c8: i3c@80700400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80700400 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c9: i3c@80700800 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80700800 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c10: i3c@80780400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80780400 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c11: i3c@80780800 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80780800 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c12: i3c@80800400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80800400 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c13: i3c@80800800 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80800800 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c14: i3c@80880400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80880400 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c15: i3c@80880800 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80880800 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c16: i3c@80620400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x00 0x80620400 0x00 0x400>;
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@80520000 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x00 0x80520000 0x00 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ uart1: serial@805a0000 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x00 0x805A0000 0x00 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ uart2: serial@80620000 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x00 0x80620000 0x00 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ uart3: serial@80520800 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x00 0x80520800 0x00 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 09/10] arm64: defconfig: enable the Axiado family
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
` (7 preceding siblings ...)
2025-07-22 20:15 ` [PATCH v6 08/10] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-22 20:15 ` [PATCH v6 10/10] MAINTAINERS: Add entry for Axiado Harshit Shah
2025-07-23 8:25 ` [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Bartosz Golaszewski
10 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah, Krzysztof Kozlowski
Enable the Axiado SoC family in the arm64 defconfig.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 897fc686e6a91b79770639d3eb15beb3ee48ef77..96268ade08aff844ad833c18397932a059db5499 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_ALPINE=y
CONFIG_ARCH_APPLE=y
+CONFIG_ARCH_AXIADO=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM2835=y
CONFIG_ARCH_BCM_IPROC=y
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 10/10] MAINTAINERS: Add entry for Axiado
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
` (8 preceding siblings ...)
2025-07-22 20:15 ` [PATCH v6 09/10] arm64: defconfig: enable the Axiado family Harshit Shah
@ 2025-07-22 20:15 ` Harshit Shah
2025-07-23 8:25 ` [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Bartosz Golaszewski
10 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-22 20:15 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann, Catalin Marinas, Will Deacon,
soc
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-gpio, Jan Kotas,
linux-serial, linux-i3c, Harshit Shah, Krzysztof Kozlowski
Add entry for Axiado maintainer and related files
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c1d245bf7b84f8a78b811e0c9c5a3edc09edc22..7a04bee308cda1d8079ef61d1c0c68bafa89fa12 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2414,6 +2414,14 @@ F: arch/arm/boot/dts/aspeed/
F: arch/arm/mach-aspeed/
N: aspeed
+ARM/AXIADO ARCHITECTURE
+M: Harshit Shah <hshah@axiado.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/arm/axiado.yaml
+F: arch/arm64/boot/dts/axiado/
+N: axiado
+
ARM/AXM LSI SOC
M: Krzysztof Kozlowski <krzk@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support
2025-07-22 20:15 [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Harshit Shah
` (9 preceding siblings ...)
2025-07-22 20:15 ` [PATCH v6 10/10] MAINTAINERS: Add entry for Axiado Harshit Shah
@ 2025-07-23 8:25 ` Bartosz Golaszewski
2025-07-23 17:53 ` Harshit Shah
10 siblings, 1 reply; 15+ messages in thread
From: Bartosz Golaszewski @ 2025-07-23 8:25 UTC (permalink / raw)
To: Harshit Shah
Cc: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij, Arnd Bergmann,
Catalin Marinas, Will Deacon, soc, devicetree, linux-kernel,
linux-arm-kernel, linux-gpio, Jan Kotas, linux-serial, linux-i3c,
Krzysztof Kozlowski
On Tue, Jul 22, 2025 at 10:16 PM Harshit Shah <hshah@axiado.com> wrote:
>
> -------------------------------
> Hello SoC maintainers,
>
> This patch series adds initial support for the Axiado AX3000 SoC and its
> evaluation board.
>
> Change from v6
> - Ran "b4 trailer -u" and add reviewed by Krzysztof
>
> Add soc@lists.linux.dev in the to list and send this series again as per
> suggestion by Krzysztof and Arnd. Thank you.
>
> Checked locally and able to apply these patchset to soc git.
> (git/soc/soc.git, for-next, checked commit: 7dfbf3176d886ff9a0c7786942d3a89809d0641e)
>
> Sorry for late request, please consider this series for the 6.17.
>
I can't speak for the rest but do you want me to take the GPIO
dt-bindings patches through the GPIO tree for v6.17 separately?
Bartosz
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support
2025-07-23 8:25 ` [PATCH v6 00/10] Axiado AX3000 SoC and Evaluation Board Support Bartosz Golaszewski
@ 2025-07-23 17:53 ` Harshit Shah
0 siblings, 0 replies; 15+ messages in thread
From: Harshit Shah @ 2025-07-23 17:53 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Greg Kroah-Hartman, Jiri Slaby, Michal Simek, Przemysław Gaj,
Alexandre Belloni, Frank Li, Boris Brezillon, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij, Arnd Bergmann,
Catalin Marinas, Will Deacon, soc@lists.linux.dev,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
Jan Kotas, linux-serial@vger.kernel.org,
linux-i3c@lists.infradead.org, Krzysztof Kozlowski, Arnd Bergmann
On 7/23/2025 1:25 AM, Bartosz Golaszewski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On Tue, Jul 22, 2025 at 10:16 PM Harshit Shah <hshah@axiado.com> wrote:
>> -------------------------------
>> Hello SoC maintainers,
>>
>> This patch series adds initial support for the Axiado AX3000 SoC and its
>> evaluation board.
>>
>> Change from v6
>> - Ran "b4 trailer -u" and add reviewed by Krzysztof
>>
>> Add soc@lists.linux.dev in the to list and send this series again as per
>> suggestion by Krzysztof and Arnd. Thank you.
>>
>> Checked locally and able to apply these patchset to soc git.
>> (git/soc/soc.git, for-next, checked commit: 7dfbf3176d886ff9a0c7786942d3a89809d0641e)
>>
>> Sorry for late request, please consider this series for the 6.17.
>>
> I can't speak for the rest but do you want me to take the GPIO
> dt-bindings patches through the GPIO tree for v6.17 separately?
Arnd has already applied this series to soc tree.
Thank you Bartosz.
Regards,
Harshit.
^ permalink raw reply [flat|nested] 15+ messages in thread