From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: mbrugger@suse.com, chester62515@gmail.com,
ghennadi.procopciuc@oss.nxp.com, shawnguo@kernel.org,
s.hauer@pengutronix.de
Cc: s32@nxp.com, kernel@pengutronix.de, festevam@gmail.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>,
Thomas Fossati <thomas.fossati@linaro.org>
Subject: [PATCH v2 3/8] arm64: dts: s32g3: Add the System Timer Module nodes
Date: Thu, 31 Jul 2025 16:01:36 +0200 [thread overview]
Message-ID: <20250731140146.62960-4-daniel.lezcano@linaro.org> (raw)
In-Reply-To: <20250731140146.62960-1-daniel.lezcano@linaro.org>
The s32g3 has a STM module containing 12 timers. Each timer has a
dedicated interrupt and share the same clock.
Add the STM0->STM11 nodes for the s32g3 SoC. The STM7 node is not
added because it is slightly different and needs an extra property
which will be added later when supported by the driver.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Cc: Thomas Fossati <thomas.fossati@linaro.org>
---
arch/arm64/boot/dts/freescale/s32g3.dtsi | 99 ++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 991dbfbfa203..c2c986f03986 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -374,6 +374,42 @@ usdhc0-200mhz-grp4 {
};
};
+ stm0: timer@4011c000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x4011c000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ stm1: timer@40120000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x40120000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ stm2: timer@40124000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x40124000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ stm3: timer@40128000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x40128000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
edma0: dma-controller@40144000 {
compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
reg = <0x40144000 0x24000>,
@@ -471,6 +507,33 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
+ stm4: timer@4021c000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x4021c000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ stm5: timer@40220000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x40220000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ stm6: timer@40224000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x40224000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
edma1: dma-controller@40244000 {
compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
reg = <0x40244000 0x24000>,
@@ -560,6 +623,42 @@ usdhc0: mmc@402f0000 {
status = "disabled";
};
+ stm8: timer@40520000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x40520000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ stm9: timer@40524000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x40524000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ stm10: timer@40528000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x40528000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ stm11: timer@4052c000 {
+ compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
+ reg = <0x4052c000 0x3000>;
+ clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
+ clock-names = "counter", "module", "register";
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.43.0
next prev parent reply other threads:[~2025-07-31 14:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-31 14:01 [PATCH v2 0/8] Add the STM and the SWT nodes for the s32g2 and s32g3 Daniel Lezcano
2025-07-31 14:01 ` [PATCH v2 1/8] arm64: dts: s32g2: Add the System Timer Module nodes Daniel Lezcano
2025-07-31 14:01 ` [PATCH v2 2/8] arm64: dts: s32g274-rd2: Enable the STM timers Daniel Lezcano
2025-07-31 14:01 ` Daniel Lezcano [this message]
2025-07-31 14:01 ` [PATCH v2 4/8] arm64: dts: s32g399a-rdb3: " Daniel Lezcano
2025-07-31 14:01 ` [PATCH v2 5/8] arm64: dts: s32g2: Add the Software Timer Watchdog (SWT) nodes Daniel Lezcano
2025-07-31 14:01 ` [PATCH v2 6/8] arm64: dts: s32g274-rd2: Enable the SWT watchdog Daniel Lezcano
2025-07-31 14:01 ` [PATCH v2 7/8] arm64: dts: s32g3: Add the Software Timer Watchdog (SWT) nodes Daniel Lezcano
2025-07-31 14:01 ` [PATCH v2 8/8] arm64: dts: s32g399a-rdb3: Enable the SWT watchdog Daniel Lezcano
2025-08-22 8:26 ` [PATCH v2 0/8] Add the STM and the SWT nodes for the s32g2 and s32g3 Shawn Guo
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