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Sun, 3 Aug 2025 21:16:59 -0700 From: Prathamesh Shete To: , , , , , , , , , , CC: Subject: [PATCH 1/2] dt-bindings: gpio: Add Tegra256 support Date: Mon, 4 Aug 2025 09:46:56 +0530 Message-ID: <20250804041657.27688-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001504:EE_|LV5PR12MB9777:EE_ X-MS-Office365-Filtering-Correlation-Id: c8816e4c-2cdc-4342-f37c-08ddd30dca80 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?w+PMBYAUE6v2oSr58v7n+HXYb05jiRzic1sY+M14Dd+tAWjep/Ih2mQmVKDT?= =?us-ascii?Q?0eX51iFWUkB3CH0ptnDq76BE+zykQhcCFpC5Ww5KzQaBGabev8Mt3HPtxx90?= =?us-ascii?Q?YMblJ7dtyH7ZgVvmK95F1HeSKyPxNa27inm+nXNxvZis1hkvfMnz8aTgn/pv?= =?us-ascii?Q?mYqJpOW6NL3L36dWnFjaGQBGcvGprlIE5hrlphahogDy06NH73nd6pAaCZti?= =?us-ascii?Q?O/7nQDQkPZ/4oQjx0q4TnAl7X63L7gkQBVYWXPiswd+qIzerDpA2U3LueSvO?= =?us-ascii?Q?0yLxk3sd2+ZB8MQjxGhpHKr/kDNQHMaXFCx2UTEbqJAMPXI+vWvswfFoaqe4?= =?us-ascii?Q?szQttkqE9DY30yuOmzS6BTWq/cvuUuKoB58SohBb9+pXbCUVN47QiiBOOGlj?= =?us-ascii?Q?iYqgYw3k1L9rb4A+z0vIQjH0P+abDvYQUZ6+ER9lqgJypLpcfSANIs1PLQGf?= =?us-ascii?Q?z+4pFVu3P7ReEMbZXYvcsYRkYj1SBdrPuJoTvuVGXeLdCuMVw3u6VQZVAFVi?= =?us-ascii?Q?LElS/Flyd74rUIoRemiTAmtc6dn05OoEGpddCP1uJ9dnbf1T608gXioHiRkq?= =?us-ascii?Q?MxdDcnUAtAWh+lbmy5uczRc4RRUYs7riuSfMItbIVYyEucVCEfXSOtkg9wO4?= =?us-ascii?Q?Eu6+nq2JTKrsdq00JTtCRl5pBORQNKUDHZs/KPvMNpL++tiGZJWYH4GoXq5o?= =?us-ascii?Q?KIhgxF3RVZEk4OeIl1r0bRR9Q4k+yedcpxz3D1JDmsvhBX0wiPWp27q6iUPK?= =?us-ascii?Q?c8mP8KUBc9fCYFHGh2aJqPZZU3WG5SpkyBeXeEbSBHDh96WvDuzVfKAtE4Z+?= =?us-ascii?Q?ZMK7qELrop7w9bw+LbupZe/F0hJ/jSOgEBceQ68EvUSQbIEsrNgINAJ52kRv?= =?us-ascii?Q?aNOnohhuC/2lN8iUMiTLPmQ2fqnk4rMuHEMykMjvFe37TQRiNw6oX+tEZOfP?= =?us-ascii?Q?2sK9kQwliy2dBxDynB+8ueifhQrbPUT4N7zo4aQrfI/QJhDBqYKUmzMpJwQy?= =?us-ascii?Q?HiFEpe108lQVNbH+0BoXRa21zp462GNtLxA4P3GVMRQ6X4c87iqcPWHx1Vb3?= =?us-ascii?Q?jdupVKW6NcKY2Jfoja7a4SQA4NP25mMVBaNhtoHiQOas1AKQ17mafQRET8y6?= =?us-ascii?Q?oo7UKZjpn45/eh02v6r5pTHdGUyQx98m15VH+TBUqeSgNoh1yYojlhCbx/sf?= =?us-ascii?Q?ltFeteUFpfrLEPpNl1oERevsQz60WoEOjFCYRLwGhscxCFU0+kBrLtmPPPpx?= =?us-ascii?Q?o9GzQdub7pGbpYXm38dgZA1n3cK5AtlDPnz5yEiaywSM0/KZUMyRxuhdvaPg?= =?us-ascii?Q?g9kICeMG4H31enPTptc3QDzttVcH7uousbaXYmQmYg+33I8AUH5xUGWrWYi1?= =?us-ascii?Q?oXiuMU2NMt+ginndMgaO2p3iHTPW6Wms9nBKZBTsLy5ELWJ2RMEy+IfNVZIY?= =?us-ascii?Q?l7MV+daBdpCCF7kKZSsHEIaqUE/2thFhQOATFCIzrZcMx2QTJKAMbXTgJtyu?= =?us-ascii?Q?0FwfSv76F2oYP4khP6sLDMbnd+j1A6Ts+CeCThaPPGJMMo6Fuqmfjb7mkA?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 04:17:14.0956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8816e4c-2cdc-4342-f37c-08ddd30dca80 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001504.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9777 Extend the existing Tegra186 GPIO controller device tree bindings with support for the GPIO controller found on Tegra256. The number of pins is slightly different, but the programming model remains the same Signed-off-by: Prathamesh Shete --- .../bindings/gpio/nvidia,tegra186-gpio.yaml | 2 ++ include/dt-bindings/gpio/tegra256-gpio.h | 28 +++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 include/dt-bindings/gpio/tegra256-gpio.h diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml index 065f5761a93f..2bd620a1099b 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml @@ -85,6 +85,7 @@ properties: - nvidia,tegra194-gpio-aon - nvidia,tegra234-gpio - nvidia,tegra234-gpio-aon + - nvidia,tegra256-gpio reg-names: items: @@ -155,6 +156,7 @@ allOf: - nvidia,tegra186-gpio - nvidia,tegra194-gpio - nvidia,tegra234-gpio + - nvidia,tegra256-gpio then: properties: interrupts: diff --git a/include/dt-bindings/gpio/tegra256-gpio.h b/include/dt-bindings/gpio/tegra256-gpio.h new file mode 100644 index 000000000000..36485b4bf47d --- /dev/null +++ b/include/dt-bindings/gpio/tegra256-gpio.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ + +/* + ** This header provides constants for binding nvidia,tegra256-gpio*. + ** + ** The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + ** provide names for this. + ** + ** The second cell contains standard flag values specified in gpio.h. + **/ + +#ifndef _DT_BINDINGS_GPIO_TEGRA256_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA256_GPIO_H + +#include + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA256_MAIN_GPIO_PORT_A 0 +#define TEGRA256_MAIN_GPIO_PORT_B 1 +#define TEGRA256_MAIN_GPIO_PORT_C 2 +#define TEGRA256_MAIN_GPIO_PORT_D 3 + +#define TEGRA256_MAIN_GPIO(port, offset) \ + ((TEGRA256_MAIN_GPIO_PORT_##port * 8) + (offset)) + +#endif + -- 2.17.1