From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD7FD4685; Mon, 4 Aug 2025 05:39:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754285997; cv=none; b=Nvf5oblFNKqLsHwJS+MSSl4iZlrWrCUxK0r1NvEvxgYZCBAuNHzu21CD7z0NDxVQYPYRADQyfcg9sC/kMUYcwGWnWAwObbGDyt3blxcvWEpKauyoOfaIX9igyBVwXBExR6sW1RHRLYHksgIWm3OL0Na4+juria+12gtyWHKCu/A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754285997; c=relaxed/simple; bh=bhfHogJ8k+Oh4dZKGTCy3obIk3sq1GLgq405nsEW8qI=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=gZLFOfyuMaB+ZQxsNbwwUv96eZyOwByaAupeF3n3P6Zs4R1wWR5T6TjRxkiYohJA2/kPyTTOMdzs8pYHJOR01xGc3EkuZsyLyORveW8vh4a9hFB9RkIg+klU7/z23wSGASjPJhRDhK6G0tbF9BNrH0RB4V1e4uXPBwElZAj4e2M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 4 Aug 2025 13:34:45 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 4 Aug 2025 13:34:45 +0800 From: Ryan Chen To: ryan_chen , Eddie James , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , , , Subject: [PATCH 0/2] irqchip: Add support for Aspeed AST2700 SCU interrupt controller Date: Mon, 4 Aug 2025 13:34:43 +0800 Message-ID: <20250804053445.1482749-1-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain This patch series adds support for the SCU (System Control Unit) interrupt controllers found in the Aspeed AST2700 SoC. The AST2700 integrates multiple SCU interrupt groups, architecturally similar to those in the AST2600, but using split registers for interrupt enable (IER) and interrupt status (ISR), whereas AST2600 uses combined registers. Ryan Chen (2): dt-bindings: interrupt-controller: aspeed: add AST2700 SCU IC compatibles irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllers .../aspeed,ast2500-scu-ic.yaml | 6 +- drivers/irqchip/irq-aspeed-scu-ic.c | 240 ++++++++++++++---- 2 files changed, 200 insertions(+), 46 deletions(-) -- 2.34.1