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From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: linux-renesas-soc@vger.kernel.org
Cc: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>,
	Wolfram Sang <wsa+renesas@sang-engineering.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	devicetree@vger.kernel.org
Subject: [PATCH 2/4] arm64: dts: renesas: r9a09g047: Add I3C node
Date: Thu,  7 Aug 2025 17:14:36 +0200	[thread overview]
Message-ID: <20250807151434.5241-8-wsa+renesas@sang-engineering.com> (raw)
In-Reply-To: <20250807151434.5241-6-wsa+renesas@sang-engineering.com>

From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Add the I3C node to RZ/G3E SoC DTSI.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index e4fac7e0d764..d2e5f5980185 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -601,6 +601,41 @@ i2c8: i2c@11c01000 {
 			status = "disabled";
 		};
 
+		i3c0: i3c@12400000 {
+			compatible = "renesas,r9a09g047-i3c";
+			reg = <0 0x12400000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0x91>,
+				 <&cpg CPG_MOD 0x92>,
+				 <&cpg CPG_MOD 0x90>;
+			clock-names = "pclk", "tclk", "pclkrw";
+			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ierr", "terr", "abort", "resp",
+					  "cmd", "ibi", "rx", "tx", "rcv",
+					  "st", "sp", "tend", "nack", "al",
+					  "tmo", "wu";
+			resets = <&cpg 0x96>, <&cpg 0x97>;
+			reset-names = "presetn", "tresetn";
+			power-domains = <&cpg>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		gpu: gpu@14850000 {
 			compatible = "renesas,r9a09g047-mali",
 				     "arm,mali-bifrost";
-- 
2.47.2


  parent reply	other threads:[~2025-08-07 15:14 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-07 15:14 [PATCH 0/4] arm64: dts: renesas: Enable I3C on RZ G3S/E Wolfram Sang
2025-08-07 15:14 ` [PATCH 1/4] arm64: dts: renesas: r9a08g045: Add I3C node Wolfram Sang
2025-08-09  5:05   ` Claudiu Beznea
2025-08-18 12:10   ` Geert Uytterhoeven
2025-08-07 15:14 ` Wolfram Sang [this message]
2025-08-12  7:26   ` [PATCH 2/4] arm64: dts: renesas: r9a09g047: " Geert Uytterhoeven
2025-08-18 12:24   ` Geert Uytterhoeven
2025-08-07 15:14 ` [PATCH 3/4] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C Wolfram Sang
2025-08-09  5:09   ` Claudiu Beznea
2025-08-09  9:17     ` Wolfram Sang
2025-08-07 15:14 ` [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: " Wolfram Sang
2025-08-07 15:52   ` Biju Das
2025-08-07 17:00     ` wsa+renesas
2025-08-07 17:34       ` Biju Das
2025-08-08 14:55   ` kernel test robot

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