From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79351284B58; Tue, 12 Aug 2025 13:51:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006682; cv=none; b=AZgpwcDPyyRt7XQ99u6dctpvkHJC8P4/2GiYUNaRCdNdhDfYk/Z0x5ySsZj+1uCvYkin4vzQn5vU8zLYNeyaLCBotdKn8bQWAllc3FuQh3Kc6xoImInDYy9kNlqltPLGvZ12jtBLK3dMUzoXyYG6keUK6WTI3b4GAztmff1rOmc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006682; c=relaxed/simple; bh=OYdOTPp/WleG/23x+u2iGWLmZo8oqF7YKe5sSXtY4gI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=dfP6TzbZOEdPgIf9/iPGBI+8z64m2lC1Rn/BIQgq4TZJMB+mdSbXnGBZPNCowaRJQfYAW/SPQJGXBY4WgTVzDZqbVB2QwiN0wbuZFFyqY5/KGPIk8BTVjCae6GJ7E3z4mf3n4uxXyl1yNENMyG5N8kHhJ8NihFprxNc7eV00JGw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=hNbYqjuw; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="hNbYqjuw" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57CDRMS6015833; Tue, 12 Aug 2025 15:50:58 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= kyXtN74VkBaQLErnP6Oirfq2yZX1obNwJfBjqV4IEtw=; b=hNbYqjuwH5xRxzy0 bHTmCU7hzteq17vcbXPKqYGqC5MVQ5/Qsi1IChhY90UNQfEPCnmNJW1WerJLG0kS 6DLLUDqGse8laVA6FYtLgLHCkNk80OS5XZyhDB+L0GH4aZ93eOHykAidvK8qdvjI GvL0iea4dhHDehiql7nOsUDk2Kd2shFqS6pKaio38+DV5Cj3w/8KLwXkCyVGN5XP c6gtPcnq/vJuZKmC3k5Wvn98BqOr73o9lYhepgf6H1LgHYYetOfp/bb/qMTPr6zf 8j3ghUUNKpCSeT+LupiZ1w2xqi6BdP70/OR+CWWuU0sBwRrEGSutK3HdTsQYLHgr UcewCQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48dw7gad8q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Aug 2025 15:50:58 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C31134006E; Tue, 12 Aug 2025 15:49:25 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A3C4878BFD5; Tue, 12 Aug 2025 15:49:03 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:03 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:03 +0200 Subject: [PATCH v2 06/13] dt-bindings: arm: stm32: add required #clock-cells property Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250812-drm-misc-next-v2-6-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 On STM32MP25 SoC, the syscfg peripheral provides a clock to the display subsystem through a multiplexer. Since it only provides a single clock, the cell value is 0. Doing so allows the clock consumers to reach the peripheral and gate the clock accordingly. Reviewed-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 31 +++++++++++++++------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ed97652c84922813e94b1818c07fe8714891c089..95d2319afe235fa86974d80f89c9deeae2275232 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -36,20 +36,31 @@ properties: clocks: maxItems: 1 + "#clock-cells": + const: 0 + required: - compatible - reg -if: - properties: - compatible: - contains: - enum: - - st,stm32mp157-syscfg - - st,stm32f4-gcan -then: - required: - - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg + - st,stm32f4-gcan + then: + required: + - clocks + - if: + properties: + compatible: + const: st,stm32mp25-syscfg + then: + required: + - "#clock-cells" additionalProperties: false -- 2.25.1