From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61E632882AF; Tue, 12 Aug 2025 13:51:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006687; cv=none; b=pdW3kXXUqNqDoexXe14TxGP/uN1XgfX8pJzu7Pujy/TQ//Aw4PlJayOLLAWOKIQ5xzMu1qEiwvdbi2oAGSV8D8jqn9ZsW2YVdNwnLMmqmEfW5cd4ei0ZKeIvTa4Wol4KOLFLQsEB7+Rz7atXV1W2Gih9HjPFaclpYCHITGB9KI0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006687; c=relaxed/simple; bh=IwGU9LIefN6gNap+bCYCGT45RgyQikx5sxEdf8lwi70=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=DiP5q8dXuShVhUEhUlkByEOpefIAMU0VGNyc4zIXPKVTLFF9beoJR8kWibfPK4Tya46w5m3Ny0wQd0dYUPc4R5m+78SDtrL2NtlgkrO3gzRdRJasYCWlTCTMy7JtFlYXN6jCYIm+KsowO1QE751iMM0BFpcX77ryAoH9wIjJVi8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=zXP9an4Z; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="zXP9an4Z" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57CD1jhO006642; Tue, 12 Aug 2025 15:51:10 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= zQREU73Ww2AuSHi+YSI1jSIYYenhpdvJj73K8k6oTeg=; b=zXP9an4Z4Y6DLlGi j7wljYCYFBnKXpiKdgI9P8IOPW57Zz3MO5poKrDZywaQgGUb8uiR57AHPx8WJZ7h j1r8I82139Z4BKaiA8HpYB8Kk7d4iSamK4Iw4MXed8BDwow3+4z2Hff01rXqIU3C kSq2h6lUE5CdkCW/X3NBW3JV6HIMVArqX9FBITC7QaTvizXpg+DzTfgZgfsLLDVk K9O1rlfolFLpik0RK34TzZCxzY2SZCJX8nz+a8EB43tWVQOeZZxq2NCQkI/7h/4Z vaU9qcSEIB6abU7nljw8g+BDTFAa4ijLFTXJku8xtQv3HrUpAs07M2vfsQVwzBTs JVJt4Q== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48dw7gad9j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Aug 2025 15:51:10 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E78CC40077; Tue, 12 Aug 2025 15:49:26 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 92A2378C592; Tue, 12 Aug 2025 15:49:05 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:05 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:06 +0200 Subject: [PATCH v2 09/13] arm64: dts: st: add ltdc support on stm32mp251 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250812-drm-misc-next-v2-9-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display interfaces. Add the LTDC node. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 8d87865850a7a6e8095c36acdef83c8e3a73ae54..6e8f76aa4680d5c253bae882edc455f4e95413f3 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1052,6 +1052,18 @@ dcmipp: dcmipp@48030000 { status = "disabled"; }; + ltdc: display-controller@48010000 { + compatible = "st,stm32mp251-ltdc"; + reg = <0x48010000 0x400>; + interrupts = , + ; + clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; + clock-names = "lcd", "bus"; + resets = <&rcc LTDC_R>; + access-controllers = <&rifsc 80>; + status = "disabled"; + }; + combophy: phy@480c0000 { compatible = "st,stm32mp25-combophy"; reg = <0x480c0000 0x1000>; -- 2.25.1