* [PATCH v3 1/2] dt-bindings: pwm: fsl,vf610-ftm-pwm: Add compatible for s32g2 and s32g3
2025-08-12 20:00 [PATCH v3 0/2] Add the s32g2 and s32g3 FTM PWM support Daniel Lezcano
@ 2025-08-12 20:00 ` Daniel Lezcano
2025-08-13 17:04 ` Conor Dooley
2025-08-12 20:00 ` [PATCH v3 2/2] pwm: Add the S32G support in the Freescale FTM driver Daniel Lezcano
2025-08-14 10:54 ` [PATCH v3 0/2] Add the s32g2 and s32g3 FTM PWM support Uwe Kleine-König
2 siblings, 1 reply; 6+ messages in thread
From: Daniel Lezcano @ 2025-08-12 20:00 UTC (permalink / raw)
To: ukleinek, robh, krzk+dt, conor+dt, Frank.Li
Cc: linux-pwm, devicetree, linux-kernel, Ghennadi.Procopciuc, s32
The S32G2 and S32G3 have a FlexTimer (FTM) available which is the same
as the one found on the Vybrid Family and the i.MX8.
Add the compatibles in the bindings
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml b/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml
index 7f9f72d95e7a..c7a10180208e 100644
--- a/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml
@@ -26,9 +26,14 @@ maintainers:
properties:
compatible:
- enum:
- - fsl,vf610-ftm-pwm
- - fsl,imx8qm-ftm-pwm
+ oneOf:
+ - enum:
+ - fsl,vf610-ftm-pwm
+ - fsl,imx8qm-ftm-pwm
+ - nxp,s32g2-ftm-pwm
+ - items:
+ - const: nxp,s32g3-ftm-pwm
+ - const: nxp,s32g2-ftm-pwm
reg:
maxItems: 1
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 2/2] pwm: Add the S32G support in the Freescale FTM driver
2025-08-12 20:00 [PATCH v3 0/2] Add the s32g2 and s32g3 FTM PWM support Daniel Lezcano
2025-08-12 20:00 ` [PATCH v3 1/2] dt-bindings: pwm: fsl,vf610-ftm-pwm: Add compatible for s32g2 and s32g3 Daniel Lezcano
@ 2025-08-12 20:00 ` Daniel Lezcano
2025-08-14 10:54 ` [PATCH v3 0/2] Add the s32g2 and s32g3 FTM PWM support Uwe Kleine-König
2 siblings, 0 replies; 6+ messages in thread
From: Daniel Lezcano @ 2025-08-12 20:00 UTC (permalink / raw)
To: ukleinek, robh, krzk+dt, conor+dt, Frank.Li
Cc: linux-pwm, devicetree, linux-kernel, Ghennadi.Procopciuc, s32
From: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com>
The Automotive S32G2 and S32G3 platforms include two FTM timers for
pwm. Each FTM has 6 PWM channels.
The current Freescale FTM driver supports the iMX8 and the Vybrid
Family FTM IP. The FTM IP found on the S32G platforms is almost
identical except for the number of channels and the register mapping.
These changes allow to deal with different number of channels and
support the holes found in the register memory mapping for s32gx for
suspend / resume. The fault register does not exist on the s32gx and
at resume time all the mapping is wrote back leading to a kernel
crash.
/* restore all registers from cache */
regcache_cache_only(fpc->regmap, false);
regcache_sync(fpc->regmap);
The regmap callbacks 'writeable_reg()' and 'readable_reg()' will skip
the address corresponding to a register which is not present.
Tested on a s32g274-rdb2 J5 PWM pin output with signal visualization
on oscilloscope.
Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com>
Co-developed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/pwm/pwm-fsl-ftm.c | 35 +++++++++++++++++++++++++++++++++--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index c45a5fca4cbb..e0069dbdb02d 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -3,6 +3,7 @@
* Freescale FlexTimer Module (FTM) PWM Driver
*
* Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2020-2025 NXP
*/
#include <linux/clk.h>
@@ -31,6 +32,8 @@ enum fsl_pwm_clk {
struct fsl_ftm_soc {
bool has_enable_bits;
+ bool has_flt_reg;
+ unsigned int npwm;
};
struct fsl_pwm_periodcfg {
@@ -386,6 +389,20 @@ static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
return false;
}
+static bool fsl_pwm_is_reg(struct device *dev, unsigned int reg)
+{
+ struct pwm_chip *chip = dev_get_drvdata(dev);
+ struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
+
+ if (reg >= FTM_CSC(fpc->soc->npwm) && reg < FTM_CNTIN)
+ return false;
+
+ if ((reg == FTM_FLTCTRL || reg == FTM_FLTPOL) && !fpc->soc->has_flt_reg)
+ return false;
+
+ return true;
+}
+
static const struct regmap_config fsl_pwm_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -394,23 +411,26 @@ static const struct regmap_config fsl_pwm_regmap_config = {
.max_register = FTM_PWMLOAD,
.volatile_reg = fsl_pwm_volatile_reg,
.cache_type = REGCACHE_FLAT,
+ .writeable_reg = fsl_pwm_is_reg,
+ .readable_reg = fsl_pwm_is_reg,
};
static int fsl_pwm_probe(struct platform_device *pdev)
{
+ const struct fsl_ftm_soc *soc = of_device_get_match_data(&pdev->dev);
struct pwm_chip *chip;
struct fsl_pwm_chip *fpc;
void __iomem *base;
int ret;
- chip = devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*fpc));
+ chip = devm_pwmchip_alloc(&pdev->dev, soc->npwm, sizeof(*fpc));
if (IS_ERR(chip))
return PTR_ERR(chip);
fpc = to_fsl_chip(chip);
mutex_init(&fpc->lock);
- fpc->soc = of_device_get_match_data(&pdev->dev);
+ fpc->soc = soc;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -526,15 +546,26 @@ static const struct dev_pm_ops fsl_pwm_pm_ops = {
static const struct fsl_ftm_soc vf610_ftm_pwm = {
.has_enable_bits = false,
+ .has_flt_reg = true,
+ .npwm = 8,
};
static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
.has_enable_bits = true,
+ .has_flt_reg = true,
+ .npwm = 8,
+};
+
+static const struct fsl_ftm_soc s32g2_ftm_pwm = {
+ .has_enable_bits = true,
+ .has_flt_reg = false,
+ .npwm = 6,
};
static const struct of_device_id fsl_pwm_dt_ids[] = {
{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
+ { .compatible = "nxp,s32g2-ftm-pwm", .data = &s32g2_ftm_pwm },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v3 0/2] Add the s32g2 and s32g3 FTM PWM support
2025-08-12 20:00 [PATCH v3 0/2] Add the s32g2 and s32g3 FTM PWM support Daniel Lezcano
2025-08-12 20:00 ` [PATCH v3 1/2] dt-bindings: pwm: fsl,vf610-ftm-pwm: Add compatible for s32g2 and s32g3 Daniel Lezcano
2025-08-12 20:00 ` [PATCH v3 2/2] pwm: Add the S32G support in the Freescale FTM driver Daniel Lezcano
@ 2025-08-14 10:54 ` Uwe Kleine-König
2025-08-14 13:23 ` Daniel Lezcano
2 siblings, 1 reply; 6+ messages in thread
From: Uwe Kleine-König @ 2025-08-14 10:54 UTC (permalink / raw)
To: Daniel Lezcano
Cc: robh, krzk+dt, conor+dt, Frank.Li, linux-pwm, devicetree,
linux-kernel, Ghennadi.Procopciuc, s32
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Hello Daniel,
On Tue, Aug 12, 2025 at 10:00:34PM +0200, Daniel Lezcano wrote:
> The NXP Automotive platform s32g2 and s32g3 have on their board a
> FlexTimer (FTM) dedicated for the PWM. The same IP is found on the
> Freescale Vybrid Family and the i.MX8 SoCs. However, there is a small
> difference with some registers not available on the s32g2/3 and 6
> channels instead of 8.
>
> These two patches provide the DT bindings for the s32g2/3 compatible
> strings and the code to deal with the FTM difference.
>
> Changelog:
> v3:
> - Fixed dt-bindings subject prefix
> v2:
> - Merged the two booleans for the regmap holes check
> - Clarified why this is needed in the changelog
> v1:
> - Initial post
>
> Daniel Lezcano (1):
> dt-bindings: pwm: fsl,vf610-ftm-pwm: Add compatible for s32g2 and
> s32g3
>
> Ghennadi Procopciuc (1):
> pwm: Add the S32G support in the Freescale FTM driver
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux.git pwm/for-next
with this merge conflict resolution:
diff --cc drivers/pwm/pwm-fsl-ftm.c
index 6683931872fc,e0069dbdb02d..000000000000
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@@ -396,7 -428,9 +416,7 @@@ static int fsl_pwm_probe(struct platfor
return PTR_ERR(chip);
fpc = to_fsl_chip(chip);
- mutex_init(&fpc->lock);
-
- fpc->soc = of_device_get_match_data(&pdev->dev);
+ fpc->soc = soc;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
The pro tip here to make your upstream maintainer lucky is to work on
their tree or next or at least the latest development release and make
use of `git format-patch --base`.
Best regards
Uwe
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^ permalink raw reply [flat|nested] 6+ messages in thread