* [PATCH 0/7] Add RZ/G3E support
@ 2025-08-14 18:41 Biju
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add RZ/G3E GPT support. It has multiple clocks and resets compared to
RZ/G2L. Also prescale field width and factor for calculating prescale
are different.
This patch has dependency on [1]
[1] https://lore.kernel.org/all/20250814115022.73732-1-biju.das.jz@bp.renesas.com/
Biju Das (7):
dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip
pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct
rzg2l_gpt_info
pwm: rzg2l-gpt: Add calculate_prescale() callback to struct
rzg2l_gpt_info
pwm: rzg2l-gpt: Add RZ/G3E support
arm64: dts: renesas: r9a09g047: Add GPT nodes
arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 525 ++++++++++++------
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 184 ++++++
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +
drivers/pwm/pwm-rzg2l-gpt.c | 93 +++-
4 files changed, 633 insertions(+), 182 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
@ 2025-08-14 18:41 ` Biju
2025-08-19 16:18 ` Tommaso Merciai
2025-08-20 20:29 ` Rob Herring
2025-08-14 18:41 ` [PATCH 6/7] arm64: dts: renesas: r9a09g047: Add GPT nodes Biju
2025-08-14 18:41 ` [PATCH 7/7] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board Biju
2 siblings, 2 replies; 9+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
SoC.
The GPT IP on these parts is similar to that on RZ/G2L but supports
only 8 interrupts per channel and has multiple clocks and resets.
Introduce a new compatible string `renesas,r9a09g047-gpt` for RZ/G3E.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 525 ++++++++++++------
1 file changed, 356 insertions(+), 169 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
index 13b807765a30..6250dbb200e7 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
@@ -58,11 +58,14 @@ description: |
properties:
compatible:
- items:
- - enum:
- - renesas,r9a07g044-gpt # RZ/G2{L,LC}
- - renesas,r9a07g054-gpt # RZ/V2L
- - const: renesas,rzg2l-gpt
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g044-gpt # RZ/G2{L,LC}
+ - renesas,r9a07g054-gpt # RZ/V2L
+ - const: renesas,rzg2l-gpt
+
+ - const: renesas,r9a09g047-gpt # RZ/G3E
reg:
maxItems: 1
@@ -71,179 +74,327 @@ properties:
const: 3
interrupts:
- items:
- - description: GPT32E0.GTCCRA input capture/compare match
- - description: GPT32E0.GTCCRB input capture/compare
- - description: GPT32E0.GTCCRC compare match
- - description: GPT32E0.GTCCRD compare match
- - description: GPT32E0.GTCCRE compare match
- - description: GPT32E0.GTCCRF compare match
- - description: GPT32E0.GTADTRA compare match
- - description: GPT32E0.GTADTRB compare match
- - description: GPT32E0.GTCNT overflow/GTPR compare match
- - description: GPT32E0.GTCNT underflow
- - description: GPT32E1.GTCCRA input capture/compare match
- - description: GPT32E1.GTCCRB input capture/compare
- - description: GPT32E1.GTCCRC compare match
- - description: GPT32E1.GTCCRD compare match
- - description: GPT32E1.GTCCRE compare match
- - description: GPT32E1.GTCCRF compare match
- - description: GPT32E1.GTADTRA compare match
- - description: GPT32E1.GTADTRB compare match
- - description: GPT32E1.GTCNT overflow/GTPR compare match
- - description: GPT32E1.GTCNT underflow
- - description: GPT32E2.GTCCRA input capture/compare match
- - description: GPT32E2.GTCCRB input capture/compare
- - description: GPT32E2.GTCCRC compare match
- - description: GPT32E2.GTCCRD compare match
- - description: GPT32E2.GTCCRE compare match
- - description: GPT32E2.GTCCRF compare match
- - description: GPT32E2.GTADTRA compare match
- - description: GPT32E2.GTADTRB compare match
- - description: GPT32E2.GTCNT overflow/GTPR compare match
- - description: GPT32E2.GTCNT underflow
- - description: GPT32E3.GTCCRA input capture/compare match
- - description: GPT32E3.GTCCRB input capture/compare
- - description: GPT32E3.GTCCRC compare match
- - description: GPT32E3.GTCCRD compare match
- - description: GPT32E3.GTCCRE compare match
- - description: GPT32E3.GTCCRF compare match
- - description: GPT32E3.GTADTRA compare match
- - description: GPT32E3.GTADTRB compare match
- - description: GPT32E3.GTCNT overflow/GTPR compare match
- - description: GPT32E3.GTCNT underflow
- - description: GPT32E4.GTCCRA input capture/compare match
- - description: GPT32E4.GTCCRB input capture/compare
- - description: GPT32E4.GTCCRC compare match
- - description: GPT32E4.GTCCRD compare match
- - description: GPT32E4.GTCCRE compare match
- - description: GPT32E4.GTCCRF compare match
- - description: GPT32E4.GTADTRA compare match
- - description: GPT32E4.GTADTRB compare match
- - description: GPT32E4.GTCNT overflow/GTPR compare match
- - description: GPT32E4.GTCNT underflow
- - description: GPT32E5.GTCCRA input capture/compare match
- - description: GPT32E5.GTCCRB input capture/compare
- - description: GPT32E5.GTCCRC compare match
- - description: GPT32E5.GTCCRD compare match
- - description: GPT32E5.GTCCRE compare match
- - description: GPT32E5.GTCCRF compare match
- - description: GPT32E5.GTADTRA compare match
- - description: GPT32E5.GTADTRB compare match
- - description: GPT32E5.GTCNT overflow/GTPR compare match
- - description: GPT32E5.GTCNT underflow
- - description: GPT32E6.GTCCRA input capture/compare match
- - description: GPT32E6.GTCCRB input capture/compare
- - description: GPT32E6.GTCCRC compare match
- - description: GPT32E6.GTCCRD compare match
- - description: GPT32E6.GTCCRE compare match
- - description: GPT32E6.GTCCRF compare match
- - description: GPT32E6.GTADTRA compare match
- - description: GPT32E6.GTADTRB compare match
- - description: GPT32E6.GTCNT overflow/GTPR compare match
- - description: GPT32E6.GTCNT underflow
- - description: GPT32E7.GTCCRA input capture/compare match
- - description: GPT32E7.GTCCRB input capture/compare
- - description: GPT32E7.GTCCRC compare match
- - description: GPT32E7.GTCCRD compare match
- - description: GPT32E7.GTCCRE compare match
- - description: GPT32E7.GTCCRF compare match
- - description: GPT32E7.GTADTRA compare match
- - description: GPT32E7.GTADTRB compare match
- - description: GPT32E7.GTCNT overflow/GTPR compare match
- - description: GPT32E7.GTCNT underflow
+ oneOf:
+ - items:
+ - description: GPT32E0.GTCCRA input capture/compare match
+ - description: GPT32E0.GTCCRB input capture/compare
+ - description: GPT32E0.GTCCRC compare match
+ - description: GPT32E0.GTCCRD compare match
+ - description: GPT32E0.GTCCRE compare match
+ - description: GPT32E0.GTCCRF compare match
+ - description: GPT32E0.GTADTRA compare match
+ - description: GPT32E0.GTADTRB compare match
+ - description: GPT32E0.GTCNT overflow/GTPR compare match
+ - description: GPT32E0.GTCNT underflow
+ - description: GPT32E1.GTCCRA input capture/compare match
+ - description: GPT32E1.GTCCRB input capture/compare
+ - description: GPT32E1.GTCCRC compare match
+ - description: GPT32E1.GTCCRD compare match
+ - description: GPT32E1.GTCCRE compare match
+ - description: GPT32E1.GTCCRF compare match
+ - description: GPT32E1.GTADTRA compare match
+ - description: GPT32E1.GTADTRB compare match
+ - description: GPT32E1.GTCNT overflow/GTPR compare match
+ - description: GPT32E1.GTCNT underflow
+ - description: GPT32E2.GTCCRA input capture/compare match
+ - description: GPT32E2.GTCCRB input capture/compare
+ - description: GPT32E2.GTCCRC compare match
+ - description: GPT32E2.GTCCRD compare match
+ - description: GPT32E2.GTCCRE compare match
+ - description: GPT32E2.GTCCRF compare match
+ - description: GPT32E2.GTADTRA compare match
+ - description: GPT32E2.GTADTRB compare match
+ - description: GPT32E2.GTCNT overflow/GTPR compare match
+ - description: GPT32E2.GTCNT underflow
+ - description: GPT32E3.GTCCRA input capture/compare match
+ - description: GPT32E3.GTCCRB input capture/compare
+ - description: GPT32E3.GTCCRC compare match
+ - description: GPT32E3.GTCCRD compare match
+ - description: GPT32E3.GTCCRE compare match
+ - description: GPT32E3.GTCCRF compare match
+ - description: GPT32E3.GTADTRA compare match
+ - description: GPT32E3.GTADTRB compare match
+ - description: GPT32E3.GTCNT overflow/GTPR compare match
+ - description: GPT32E3.GTCNT underflow
+ - description: GPT32E4.GTCCRA input capture/compare match
+ - description: GPT32E4.GTCCRB input capture/compare
+ - description: GPT32E4.GTCCRC compare match
+ - description: GPT32E4.GTCCRD compare match
+ - description: GPT32E4.GTCCRE compare match
+ - description: GPT32E4.GTCCRF compare match
+ - description: GPT32E4.GTADTRA compare match
+ - description: GPT32E4.GTADTRB compare match
+ - description: GPT32E4.GTCNT overflow/GTPR compare match
+ - description: GPT32E4.GTCNT underflow
+ - description: GPT32E5.GTCCRA input capture/compare match
+ - description: GPT32E5.GTCCRB input capture/compare
+ - description: GPT32E5.GTCCRC compare match
+ - description: GPT32E5.GTCCRD compare match
+ - description: GPT32E5.GTCCRE compare match
+ - description: GPT32E5.GTCCRF compare match
+ - description: GPT32E5.GTADTRA compare match
+ - description: GPT32E5.GTADTRB compare match
+ - description: GPT32E5.GTCNT overflow/GTPR compare match
+ - description: GPT32E5.GTCNT underflow
+ - description: GPT32E6.GTCCRA input capture/compare match
+ - description: GPT32E6.GTCCRB input capture/compare
+ - description: GPT32E6.GTCCRC compare match
+ - description: GPT32E6.GTCCRD compare match
+ - description: GPT32E6.GTCCRE compare match
+ - description: GPT32E6.GTCCRF compare match
+ - description: GPT32E6.GTADTRA compare match
+ - description: GPT32E6.GTADTRB compare match
+ - description: GPT32E6.GTCNT overflow/GTPR compare match
+ - description: GPT32E6.GTCNT underflow
+ - description: GPT32E7.GTCCRA input capture/compare match
+ - description: GPT32E7.GTCCRB input capture/compare
+ - description: GPT32E7.GTCCRC compare match
+ - description: GPT32E7.GTCCRD compare match
+ - description: GPT32E7.GTCCRE compare match
+ - description: GPT32E7.GTCCRF compare match
+ - description: GPT32E7.GTADTRA compare match
+ - description: GPT32E7.GTADTRB compare match
+ - description: GPT32E7.GTCNT overflow/GTPR compare match
+ - description: GPT32E7.GTCNT underflow
+ - items:
+ - description: Input capture/compare match of the GTCCRA for channel 0 and 8
+ - description: Input capture/compare match of the GTCCRB for channel 0 and 8
+ - description: Compare match with the GTCCRC for channel 0 and 8
+ - description: Compare match with the GTCCRD for channel 0 and 8
+ - description: Compare match with the GTCCRE for channel 0 and 8
+ - description: Compare match with the GTCCRF for channel 0 and 8
+ - description: A and B both high interrupt for channel 0 and 8
+ - description: A and B both low interrupt for channel 0 and 8
+ - description: Input capture/compare match of the GTCCRA for channel 1 and 9
+ - description: Input capture/compare match of the GTCCRB for channel 1 and 9
+ - description: Compare match with the GTCCRC for channel 1 and 9
+ - description: Compare match with the GTCCRD for channel 1 and 9
+ - description: Compare match with the GTCCRE for channel 1 and 9
+ - description: Compare match with the GTCCRF for channel 1 and 9
+ - description: A and B both high interrupt for channel 1 and 9
+ - description: A and B both low interrupt for channel 1 and 9
+ - description: Input capture/compare match of the GTCCRA for channel 2 and 10
+ - description: Input capture/compare match of the GTCCRB for channel 2 and 10
+ - description: Compare match with the GTCCRC for channel 2 and 10
+ - description: Compare match with the GTCCRD for channel 2 and 10
+ - description: Compare match with the GTCCRE for channel 2 and 10
+ - description: Compare match with the GTCCRF for channel 2 and 10
+ - description: A and B both high interrupt for channel 2 and 10
+ - description: A and B both low interrupt for channel 2 and 10
+ - description: Input capture/compare match of the GTCCRA for channel 3 and 11
+ - description: Input capture/compare match of the GTCCRB for channel 3 and 11
+ - description: Compare match with the GTCCRC for channel 3 and 11
+ - description: Compare match with the GTCCRD for channel 3 and 11
+ - description: Compare match with the GTCCRE for channel 3 and 11
+ - description: Compare match with the GTCCRF for channel 3 and 11
+ - description: A and B both high interrupt for channel 3 and 11
+ - description: A and B both low interrupt for channel 3 and 11
+ - description: Input capture/compare match of the GTCCRA for channel 4 and 12
+ - description: Input capture/compare match of the GTCCRB for channel 4 and 12
+ - description: Compare match with the GTCCRC for channel 4 and 12
+ - description: Compare match with the GTCCRD for channel 4 and 12
+ - description: Compare match with the GTCCRE for channel 4 and 12
+ - description: Compare match with the GTCCRF for channel 4 and 12
+ - description: A and B both high interrupt for channel 4 and 12
+ - description: A and B both low interrupt for channel 4 and 12
+ - description: Input capture/compare match of the GTCCRA for channel 5 and 13
+ - description: Input capture/compare match of the GTCCRB for channel 5 and 13
+ - description: Compare match with the GTCCRC for channel 5 and 13
+ - description: Compare match with the GTCCRD for channel 5 and 13
+ - description: Compare match with the GTCCRE for channel 5 and 13
+ - description: Compare match with the GTCCRF for channel 5 and 13
+ - description: A and B both high interrupt for channel 5 and 13
+ - description: A and B both low interrupt for channel 5 and 13
+ - description: Input capture/compare match of the GTCCRA for channel 6 and 14
+ - description: Input capture/compare match of the GTCCRB for channel 6 and 14
+ - description: Compare match with the GTCCRC for channel 6 and 14
+ - description: Compare match with the GTCCRD for channel 6 and 14
+ - description: Compare match with the GTCCRE for channel 6 and 14
+ - description: Compare match with the GTCCRF for channel 6 and 14
+ - description: A and B both high interrupt for channel 6 and 14
+ - description: A and B both low interrupt for channel 6 and 14
+ - description: Input capture/compare match of the GTCCRA for channel 7 and 15
+ - description: Input capture/compare match of the GTCCRB for channel 7 and 15
+ - description: Compare match with the GTCCRC for channel 7 and 15
+ - description: Compare match with the GTCCRD for channel 7 and 15
+ - description: Compare match with the GTCCRE for channel 7 and 15
+ - description: Compare match with the GTCCRF for channel 7 and 15
+ - description: A and B both high interrupt for channel 7 and 15
+ - description: A and B both low interrupt for channel 7 and 15
interrupt-names:
- items:
- - const: ccmpa0
- - const: ccmpb0
- - const: cmpc0
- - const: cmpd0
- - const: cmpe0
- - const: cmpf0
- - const: adtrga0
- - const: adtrgb0
- - const: ovf0
- - const: unf0
- - const: ccmpa1
- - const: ccmpb1
- - const: cmpc1
- - const: cmpd1
- - const: cmpe1
- - const: cmpf1
- - const: adtrga1
- - const: adtrgb1
- - const: ovf1
- - const: unf1
- - const: ccmpa2
- - const: ccmpb2
- - const: cmpc2
- - const: cmpd2
- - const: cmpe2
- - const: cmpf2
- - const: adtrga2
- - const: adtrgb2
- - const: ovf2
- - const: unf2
- - const: ccmpa3
- - const: ccmpb3
- - const: cmpc3
- - const: cmpd3
- - const: cmpe3
- - const: cmpf3
- - const: adtrga3
- - const: adtrgb3
- - const: ovf3
- - const: unf3
- - const: ccmpa4
- - const: ccmpb4
- - const: cmpc4
- - const: cmpd4
- - const: cmpe4
- - const: cmpf4
- - const: adtrga4
- - const: adtrgb4
- - const: ovf4
- - const: unf4
- - const: ccmpa5
- - const: ccmpb5
- - const: cmpc5
- - const: cmpd5
- - const: cmpe5
- - const: cmpf5
- - const: adtrga5
- - const: adtrgb5
- - const: ovf5
- - const: unf5
- - const: ccmpa6
- - const: ccmpb6
- - const: cmpc6
- - const: cmpd6
- - const: cmpe6
- - const: cmpf6
- - const: adtrga6
- - const: adtrgb6
- - const: ovf6
- - const: unf6
- - const: ccmpa7
- - const: ccmpb7
- - const: cmpc7
- - const: cmpd7
- - const: cmpe7
- - const: cmpf7
- - const: adtrga7
- - const: adtrgb7
- - const: ovf7
- - const: unf7
+ oneOf:
+ - items:
+ - const: ccmpa0
+ - const: ccmpb0
+ - const: cmpc0
+ - const: cmpd0
+ - const: cmpe0
+ - const: cmpf0
+ - const: adtrga0
+ - const: adtrgb0
+ - const: ovf0
+ - const: unf0
+ - const: ccmpa1
+ - const: ccmpb1
+ - const: cmpc1
+ - const: cmpd1
+ - const: cmpe1
+ - const: cmpf1
+ - const: adtrga1
+ - const: adtrgb1
+ - const: ovf1
+ - const: unf1
+ - const: ccmpa2
+ - const: ccmpb2
+ - const: cmpc2
+ - const: cmpd2
+ - const: cmpe2
+ - const: cmpf2
+ - const: adtrga2
+ - const: adtrgb2
+ - const: ovf2
+ - const: unf2
+ - const: ccmpa3
+ - const: ccmpb3
+ - const: cmpc3
+ - const: cmpd3
+ - const: cmpe3
+ - const: cmpf3
+ - const: adtrga3
+ - const: adtrgb3
+ - const: ovf3
+ - const: unf3
+ - const: ccmpa4
+ - const: ccmpb4
+ - const: cmpc4
+ - const: cmpd4
+ - const: cmpe4
+ - const: cmpf4
+ - const: adtrga4
+ - const: adtrgb4
+ - const: ovf4
+ - const: unf4
+ - const: ccmpa5
+ - const: ccmpb5
+ - const: cmpc5
+ - const: cmpd5
+ - const: cmpe5
+ - const: cmpf5
+ - const: adtrga5
+ - const: adtrgb5
+ - const: ovf5
+ - const: unf5
+ - const: ccmpa6
+ - const: ccmpb6
+ - const: cmpc6
+ - const: cmpd6
+ - const: cmpe6
+ - const: cmpf6
+ - const: adtrga6
+ - const: adtrgb6
+ - const: ovf6
+ - const: unf6
+ - const: ccmpa7
+ - const: ccmpb7
+ - const: cmpc7
+ - const: cmpd7
+ - const: cmpe7
+ - const: cmpf7
+ - const: adtrga7
+ - const: adtrgb7
+ - const: ovf7
+ - const: unf7
+ - items:
+ - const: gtcia0
+ - const: gtcib0
+ - const: gtcic0
+ - const: gtcid0
+ - const: gtcie0
+ - const: gtcif0
+ - const: gtcih0
+ - const: gtcil0
+ - const: gtcia1
+ - const: gtcib1
+ - const: gtcic1
+ - const: gtcid1
+ - const: gtcie1
+ - const: gtcif1
+ - const: gtcih1
+ - const: gtcil1
+ - const: gtcia2
+ - const: gtcib2
+ - const: gtcic2
+ - const: gtcid2
+ - const: gtcie2
+ - const: gtcif2
+ - const: gtcih2
+ - const: gtcil2
+ - const: gtcia3
+ - const: gtcib3
+ - const: gtcic3
+ - const: gtcid3
+ - const: gtcie3
+ - const: gtcif3
+ - const: gtcih3
+ - const: gtcil3
+ - const: gtcia4
+ - const: gtcib4
+ - const: gtcic4
+ - const: gtcid4
+ - const: gtcie4
+ - const: gtcif4
+ - const: gtcih4
+ - const: gtcil4
+ - const: gtcia5
+ - const: gtcib5
+ - const: gtcic5
+ - const: gtcid5
+ - const: gtcie5
+ - const: gtcif5
+ - const: gtcih5
+ - const: gtcil5
+ - const: gtcia6
+ - const: gtcib6
+ - const: gtcic6
+ - const: gtcid6
+ - const: gtcie6
+ - const: gtcif6
+ - const: gtcih6
+ - const: gtcil6
+ - const: gtcia7
+ - const: gtcib7
+ - const: gtcic7
+ - const: gtcid7
+ - const: gtcie7
+ - const: gtcif7
+ - const: gtcih7
+ - const: gtcil7
clocks:
- maxItems: 1
+ items:
+ - description: Core clock (PCLKD)
+ - description: Bus clock (PCLKA)
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: core
+ - const: bus
power-domains:
maxItems: 1
resets:
- maxItems: 1
+ items:
+ - description: Reset for bus clock (PCLKA/PCLKD)
+ - description: Reset for core clock (PCLKD)
+ minItems: 1
+
+ reset-names:
+ items:
+ - const: rst_p
+ - const: rst_s
required:
- compatible
@@ -257,6 +408,42 @@ required:
allOf:
- $ref: pwm.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g047-gpt
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ resets:
+ minItems: 2
+ interrupts:
+ maxItems: 64
+ interrupt-names:
+ maxItems: 64
+
+ required:
+ - clock-names
+ - reset-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzg2l-gpt
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ resets:
+ maxItems: 1
+ interrupts:
+ minItems: 80
+ interrupt-names:
+ minItems: 80
+
additionalProperties: false
examples:
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/7] arm64: dts: renesas: r9a09g047: Add GPT nodes
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
@ 2025-08-14 18:41 ` Biju
2025-08-19 16:24 ` Tommaso Merciai
2025-08-14 18:41 ` [PATCH 7/7] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board Biju
2 siblings, 1 reply; 9+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
The RZ/G3E SoC has 2 GPT's. Add GPT nodes to RZ/G3E ("R9A09G047") SoC
DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 184 +++++++++++++++++++++
1 file changed, 184 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index eeccd1345f71..0e6867ad112a 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -552,6 +552,190 @@ channel5 {
};
};
+ gpt0: pwm@13010000 {
+ compatible = "renesas,r9a09g047-gpt";
+ reg = <0 0x13010000 0 0x10000>;
+ #pwm-cells = <3>;
+ interrupts = <GIC_SPI 538 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 554 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 562 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 586 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 594 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 539 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 555 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 563 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 579 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 540 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 548 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 556 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 572 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 580 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 541 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 549 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 557 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 573 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 581 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 589 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 597 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 542 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 550 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 558 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 566 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 582 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 590 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 598 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 543 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 551 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 559 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 567 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 575 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 544 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 552 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 560 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 584 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 553 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 561 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 577 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 593 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
+ "gtcie0", "gtcif0", "gtcih0", "gtcil0",
+ "gtcia1", "gtcib1", "gtcic1", "gtcid1",
+ "gtcie1", "gtcif1", "gtcih1", "gtcil1",
+ "gtcia2", "gtcib2", "gtcic2", "gtcid2",
+ "gtcie2", "gtcif2", "gtcih2", "gtcil2",
+ "gtcia3", "gtcib3", "gtcic3", "gtcid3",
+ "gtcie3", "gtcif3", "gtcih3", "gtcil3",
+ "gtcia4", "gtcib4", "gtcic4", "gtcid4",
+ "gtcie4", "gtcif4", "gtcih4", "gtcil4",
+ "gtcia5", "gtcib5", "gtcic5", "gtcid5",
+ "gtcie5", "gtcif5", "gtcih5", "gtcil5",
+ "gtcia6", "gtcib6", "gtcic6", "gtcid6",
+ "gtcie6", "gtcif6", "gtcih6", "gtcil6",
+ "gtcia7", "gtcib7", "gtcic7", "gtcid7",
+ "gtcie7", "gtcif7", "gtcih7", "gtcil7";
+ clocks = <&cpg CPG_CORE R9A09G047_GPT_0_CLKS_GPT>, <&cpg CPG_MOD 0x31>;
+ clock-names = "core", "bus";
+ resets = <&cpg 0x59>, <&cpg 0x5a>;
+ reset-names = "rst_p", "rst_s";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt1: pwm@13020000 {
+ compatible = "renesas,r9a09g047-gpt";
+ reg = <0 0x13020000 0 0x10000>;
+ #pwm-cells = <3>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 610 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 618 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 626 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 642 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 658 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 627 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 659 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 628 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 636 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 652 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 660 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 613 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 621 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 629 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 637 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 661 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 614 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 622 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 630 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 646 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 662 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 631 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 647 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 663 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 632 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 656 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 609 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 617 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 625 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 633 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 665 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
+ "gtcie0", "gtcif0", "gtcih0", "gtcil0",
+ "gtcia1", "gtcib1", "gtcic1", "gtcid1",
+ "gtcie1", "gtcif1", "gtcih1", "gtcil1",
+ "gtcia2", "gtcib2", "gtcic2", "gtcid2",
+ "gtcie2", "gtcif2", "gtcih2", "gtcil2",
+ "gtcia3", "gtcib3", "gtcic3", "gtcid3",
+ "gtcie3", "gtcif3", "gtcih3", "gtcil3",
+ "gtcia4", "gtcib4", "gtcic4", "gtcid4",
+ "gtcie4", "gtcif4", "gtcih4", "gtcil4",
+ "gtcia5", "gtcib5", "gtcic5", "gtcid5",
+ "gtcie5", "gtcif5", "gtcih5", "gtcil5",
+ "gtcia6", "gtcib6", "gtcic6", "gtcid6",
+ "gtcie6", "gtcif6", "gtcih6", "gtcil6",
+ "gtcia7", "gtcib7", "gtcic7", "gtcid7",
+ "gtcie7", "gtcif7", "gtcih7", "gtcil7";
+ clocks = <&cpg CPG_CORE R9A09G047_GPT_1_CLKS_GPT>, <&cpg CPG_MOD 0x32>;
+ clock-names = "core", "bus";
+ resets = <&cpg 0x5b>, <&cpg 0x5c>;
+ reset-names = "rst_p", "rst_s";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
wdt1: watchdog@14400000 {
compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x14400000 0 0x400>;
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 7/7] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
2025-08-14 18:41 ` [PATCH 6/7] arm64: dts: renesas: r9a09g047: Add GPT nodes Biju
@ 2025-08-14 18:41 ` Biju
2025-08-19 16:25 ` Tommaso Merciai
2 siblings, 1 reply; 9+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
The GTIOC4{A,B} IOs are available on the carrier board's PMOD1_6A
connector. Enable the GPT on the carrier board by adding the GPT pinmux
and node on the carrier board dtsi file.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 1e67f0a2a945..093c0202b4f9 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -84,6 +84,14 @@ &can_transceiver1 {
};
#endif
+#if (!SW_LCD_EN) && (!SW_GPIO8_CAN0_STB)
+&gpt0 {
+ pinctrl-0 = <&gpt0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+#endif
+
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
@@ -125,6 +133,11 @@ can4_pins: can4 {
};
};
+ gpt0_pins: gpt0 {
+ pinmux = <RZG3E_PORT_PINMUX(5, 4, 10)>, /* GTIOC4A */
+ <RZG3E_PORT_PINMUX(5, 5, 10)>; /* GTIOC4B */
+ };
+
i2c0_pins: i2c0 {
pinmux = <RZG3E_PORT_PINMUX(D, 4, 4)>, /* SCL0 */
<RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
@ 2025-08-19 16:18 ` Tommaso Merciai
2025-08-20 20:29 ` Rob Herring
1 sibling, 0 replies; 9+ messages in thread
From: Tommaso Merciai @ 2025-08-19 16:18 UTC (permalink / raw)
To: Biju
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad
Hi Biju,
Thank you for the patch.
On Thu, Aug 14, 2025 at 07:41:05PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
> SoC.
>
> The GPT IP on these parts is similar to that on RZ/G2L but supports
> only 8 interrupts per channel and has multiple clocks and resets.
> Introduce a new compatible string `renesas,r9a09g047-gpt` for RZ/G3E.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 525 ++++++++++++------
> 1 file changed, 356 insertions(+), 169 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> index 13b807765a30..6250dbb200e7 100644
> --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> @@ -58,11 +58,14 @@ description: |
>
> properties:
> compatible:
> - items:
> - - enum:
> - - renesas,r9a07g044-gpt # RZ/G2{L,LC}
> - - renesas,r9a07g054-gpt # RZ/V2L
> - - const: renesas,rzg2l-gpt
> + oneOf:
> + - items:
> + - enum:
> + - renesas,r9a07g044-gpt # RZ/G2{L,LC}
> + - renesas,r9a07g054-gpt # RZ/V2L
> + - const: renesas,rzg2l-gpt
> +
> + - const: renesas,r9a09g047-gpt # RZ/G3E
>
> reg:
> maxItems: 1
> @@ -71,179 +74,327 @@ properties:
> const: 3
>
> interrupts:
> - items:
> - - description: GPT32E0.GTCCRA input capture/compare match
> - - description: GPT32E0.GTCCRB input capture/compare
> - - description: GPT32E0.GTCCRC compare match
> - - description: GPT32E0.GTCCRD compare match
> - - description: GPT32E0.GTCCRE compare match
> - - description: GPT32E0.GTCCRF compare match
> - - description: GPT32E0.GTADTRA compare match
> - - description: GPT32E0.GTADTRB compare match
> - - description: GPT32E0.GTCNT overflow/GTPR compare match
> - - description: GPT32E0.GTCNT underflow
> - - description: GPT32E1.GTCCRA input capture/compare match
> - - description: GPT32E1.GTCCRB input capture/compare
> - - description: GPT32E1.GTCCRC compare match
> - - description: GPT32E1.GTCCRD compare match
> - - description: GPT32E1.GTCCRE compare match
> - - description: GPT32E1.GTCCRF compare match
> - - description: GPT32E1.GTADTRA compare match
> - - description: GPT32E1.GTADTRB compare match
> - - description: GPT32E1.GTCNT overflow/GTPR compare match
> - - description: GPT32E1.GTCNT underflow
> - - description: GPT32E2.GTCCRA input capture/compare match
> - - description: GPT32E2.GTCCRB input capture/compare
> - - description: GPT32E2.GTCCRC compare match
> - - description: GPT32E2.GTCCRD compare match
> - - description: GPT32E2.GTCCRE compare match
> - - description: GPT32E2.GTCCRF compare match
> - - description: GPT32E2.GTADTRA compare match
> - - description: GPT32E2.GTADTRB compare match
> - - description: GPT32E2.GTCNT overflow/GTPR compare match
> - - description: GPT32E2.GTCNT underflow
> - - description: GPT32E3.GTCCRA input capture/compare match
> - - description: GPT32E3.GTCCRB input capture/compare
> - - description: GPT32E3.GTCCRC compare match
> - - description: GPT32E3.GTCCRD compare match
> - - description: GPT32E3.GTCCRE compare match
> - - description: GPT32E3.GTCCRF compare match
> - - description: GPT32E3.GTADTRA compare match
> - - description: GPT32E3.GTADTRB compare match
> - - description: GPT32E3.GTCNT overflow/GTPR compare match
> - - description: GPT32E3.GTCNT underflow
> - - description: GPT32E4.GTCCRA input capture/compare match
> - - description: GPT32E4.GTCCRB input capture/compare
> - - description: GPT32E4.GTCCRC compare match
> - - description: GPT32E4.GTCCRD compare match
> - - description: GPT32E4.GTCCRE compare match
> - - description: GPT32E4.GTCCRF compare match
> - - description: GPT32E4.GTADTRA compare match
> - - description: GPT32E4.GTADTRB compare match
> - - description: GPT32E4.GTCNT overflow/GTPR compare match
> - - description: GPT32E4.GTCNT underflow
> - - description: GPT32E5.GTCCRA input capture/compare match
> - - description: GPT32E5.GTCCRB input capture/compare
> - - description: GPT32E5.GTCCRC compare match
> - - description: GPT32E5.GTCCRD compare match
> - - description: GPT32E5.GTCCRE compare match
> - - description: GPT32E5.GTCCRF compare match
> - - description: GPT32E5.GTADTRA compare match
> - - description: GPT32E5.GTADTRB compare match
> - - description: GPT32E5.GTCNT overflow/GTPR compare match
> - - description: GPT32E5.GTCNT underflow
> - - description: GPT32E6.GTCCRA input capture/compare match
> - - description: GPT32E6.GTCCRB input capture/compare
> - - description: GPT32E6.GTCCRC compare match
> - - description: GPT32E6.GTCCRD compare match
> - - description: GPT32E6.GTCCRE compare match
> - - description: GPT32E6.GTCCRF compare match
> - - description: GPT32E6.GTADTRA compare match
> - - description: GPT32E6.GTADTRB compare match
> - - description: GPT32E6.GTCNT overflow/GTPR compare match
> - - description: GPT32E6.GTCNT underflow
> - - description: GPT32E7.GTCCRA input capture/compare match
> - - description: GPT32E7.GTCCRB input capture/compare
> - - description: GPT32E7.GTCCRC compare match
> - - description: GPT32E7.GTCCRD compare match
> - - description: GPT32E7.GTCCRE compare match
> - - description: GPT32E7.GTCCRF compare match
> - - description: GPT32E7.GTADTRA compare match
> - - description: GPT32E7.GTADTRB compare match
> - - description: GPT32E7.GTCNT overflow/GTPR compare match
> - - description: GPT32E7.GTCNT underflow
> + oneOf:
> + - items:
> + - description: GPT32E0.GTCCRA input capture/compare match
> + - description: GPT32E0.GTCCRB input capture/compare
> + - description: GPT32E0.GTCCRC compare match
> + - description: GPT32E0.GTCCRD compare match
> + - description: GPT32E0.GTCCRE compare match
> + - description: GPT32E0.GTCCRF compare match
> + - description: GPT32E0.GTADTRA compare match
> + - description: GPT32E0.GTADTRB compare match
> + - description: GPT32E0.GTCNT overflow/GTPR compare match
> + - description: GPT32E0.GTCNT underflow
> + - description: GPT32E1.GTCCRA input capture/compare match
> + - description: GPT32E1.GTCCRB input capture/compare
> + - description: GPT32E1.GTCCRC compare match
> + - description: GPT32E1.GTCCRD compare match
> + - description: GPT32E1.GTCCRE compare match
> + - description: GPT32E1.GTCCRF compare match
> + - description: GPT32E1.GTADTRA compare match
> + - description: GPT32E1.GTADTRB compare match
> + - description: GPT32E1.GTCNT overflow/GTPR compare match
> + - description: GPT32E1.GTCNT underflow
> + - description: GPT32E2.GTCCRA input capture/compare match
> + - description: GPT32E2.GTCCRB input capture/compare
> + - description: GPT32E2.GTCCRC compare match
> + - description: GPT32E2.GTCCRD compare match
> + - description: GPT32E2.GTCCRE compare match
> + - description: GPT32E2.GTCCRF compare match
> + - description: GPT32E2.GTADTRA compare match
> + - description: GPT32E2.GTADTRB compare match
> + - description: GPT32E2.GTCNT overflow/GTPR compare match
> + - description: GPT32E2.GTCNT underflow
> + - description: GPT32E3.GTCCRA input capture/compare match
> + - description: GPT32E3.GTCCRB input capture/compare
> + - description: GPT32E3.GTCCRC compare match
> + - description: GPT32E3.GTCCRD compare match
> + - description: GPT32E3.GTCCRE compare match
> + - description: GPT32E3.GTCCRF compare match
> + - description: GPT32E3.GTADTRA compare match
> + - description: GPT32E3.GTADTRB compare match
> + - description: GPT32E3.GTCNT overflow/GTPR compare match
> + - description: GPT32E3.GTCNT underflow
> + - description: GPT32E4.GTCCRA input capture/compare match
> + - description: GPT32E4.GTCCRB input capture/compare
> + - description: GPT32E4.GTCCRC compare match
> + - description: GPT32E4.GTCCRD compare match
> + - description: GPT32E4.GTCCRE compare match
> + - description: GPT32E4.GTCCRF compare match
> + - description: GPT32E4.GTADTRA compare match
> + - description: GPT32E4.GTADTRB compare match
> + - description: GPT32E4.GTCNT overflow/GTPR compare match
> + - description: GPT32E4.GTCNT underflow
> + - description: GPT32E5.GTCCRA input capture/compare match
> + - description: GPT32E5.GTCCRB input capture/compare
> + - description: GPT32E5.GTCCRC compare match
> + - description: GPT32E5.GTCCRD compare match
> + - description: GPT32E5.GTCCRE compare match
> + - description: GPT32E5.GTCCRF compare match
> + - description: GPT32E5.GTADTRA compare match
> + - description: GPT32E5.GTADTRB compare match
> + - description: GPT32E5.GTCNT overflow/GTPR compare match
> + - description: GPT32E5.GTCNT underflow
> + - description: GPT32E6.GTCCRA input capture/compare match
> + - description: GPT32E6.GTCCRB input capture/compare
> + - description: GPT32E6.GTCCRC compare match
> + - description: GPT32E6.GTCCRD compare match
> + - description: GPT32E6.GTCCRE compare match
> + - description: GPT32E6.GTCCRF compare match
> + - description: GPT32E6.GTADTRA compare match
> + - description: GPT32E6.GTADTRB compare match
> + - description: GPT32E6.GTCNT overflow/GTPR compare match
> + - description: GPT32E6.GTCNT underflow
> + - description: GPT32E7.GTCCRA input capture/compare match
> + - description: GPT32E7.GTCCRB input capture/compare
> + - description: GPT32E7.GTCCRC compare match
> + - description: GPT32E7.GTCCRD compare match
> + - description: GPT32E7.GTCCRE compare match
> + - description: GPT32E7.GTCCRF compare match
> + - description: GPT32E7.GTADTRA compare match
> + - description: GPT32E7.GTADTRB compare match
> + - description: GPT32E7.GTCNT overflow/GTPR compare match
> + - description: GPT32E7.GTCNT underflow
> + - items:
> + - description: Input capture/compare match of the GTCCRA for channel 0 and 8
> + - description: Input capture/compare match of the GTCCRB for channel 0 and 8
> + - description: Compare match with the GTCCRC for channel 0 and 8
> + - description: Compare match with the GTCCRD for channel 0 and 8
> + - description: Compare match with the GTCCRE for channel 0 and 8
> + - description: Compare match with the GTCCRF for channel 0 and 8
> + - description: A and B both high interrupt for channel 0 and 8
> + - description: A and B both low interrupt for channel 0 and 8
> + - description: Input capture/compare match of the GTCCRA for channel 1 and 9
> + - description: Input capture/compare match of the GTCCRB for channel 1 and 9
> + - description: Compare match with the GTCCRC for channel 1 and 9
> + - description: Compare match with the GTCCRD for channel 1 and 9
> + - description: Compare match with the GTCCRE for channel 1 and 9
> + - description: Compare match with the GTCCRF for channel 1 and 9
> + - description: A and B both high interrupt for channel 1 and 9
> + - description: A and B both low interrupt for channel 1 and 9
> + - description: Input capture/compare match of the GTCCRA for channel 2 and 10
> + - description: Input capture/compare match of the GTCCRB for channel 2 and 10
> + - description: Compare match with the GTCCRC for channel 2 and 10
> + - description: Compare match with the GTCCRD for channel 2 and 10
> + - description: Compare match with the GTCCRE for channel 2 and 10
> + - description: Compare match with the GTCCRF for channel 2 and 10
> + - description: A and B both high interrupt for channel 2 and 10
> + - description: A and B both low interrupt for channel 2 and 10
> + - description: Input capture/compare match of the GTCCRA for channel 3 and 11
> + - description: Input capture/compare match of the GTCCRB for channel 3 and 11
> + - description: Compare match with the GTCCRC for channel 3 and 11
> + - description: Compare match with the GTCCRD for channel 3 and 11
> + - description: Compare match with the GTCCRE for channel 3 and 11
> + - description: Compare match with the GTCCRF for channel 3 and 11
> + - description: A and B both high interrupt for channel 3 and 11
> + - description: A and B both low interrupt for channel 3 and 11
> + - description: Input capture/compare match of the GTCCRA for channel 4 and 12
> + - description: Input capture/compare match of the GTCCRB for channel 4 and 12
> + - description: Compare match with the GTCCRC for channel 4 and 12
> + - description: Compare match with the GTCCRD for channel 4 and 12
> + - description: Compare match with the GTCCRE for channel 4 and 12
> + - description: Compare match with the GTCCRF for channel 4 and 12
> + - description: A and B both high interrupt for channel 4 and 12
> + - description: A and B both low interrupt for channel 4 and 12
> + - description: Input capture/compare match of the GTCCRA for channel 5 and 13
> + - description: Input capture/compare match of the GTCCRB for channel 5 and 13
> + - description: Compare match with the GTCCRC for channel 5 and 13
> + - description: Compare match with the GTCCRD for channel 5 and 13
> + - description: Compare match with the GTCCRE for channel 5 and 13
> + - description: Compare match with the GTCCRF for channel 5 and 13
> + - description: A and B both high interrupt for channel 5 and 13
> + - description: A and B both low interrupt for channel 5 and 13
> + - description: Input capture/compare match of the GTCCRA for channel 6 and 14
> + - description: Input capture/compare match of the GTCCRB for channel 6 and 14
> + - description: Compare match with the GTCCRC for channel 6 and 14
> + - description: Compare match with the GTCCRD for channel 6 and 14
> + - description: Compare match with the GTCCRE for channel 6 and 14
> + - description: Compare match with the GTCCRF for channel 6 and 14
> + - description: A and B both high interrupt for channel 6 and 14
> + - description: A and B both low interrupt for channel 6 and 14
> + - description: Input capture/compare match of the GTCCRA for channel 7 and 15
> + - description: Input capture/compare match of the GTCCRB for channel 7 and 15
> + - description: Compare match with the GTCCRC for channel 7 and 15
> + - description: Compare match with the GTCCRD for channel 7 and 15
> + - description: Compare match with the GTCCRE for channel 7 and 15
> + - description: Compare match with the GTCCRF for channel 7 and 15
> + - description: A and B both high interrupt for channel 7 and 15
> + - description: A and B both low interrupt for channel 7 and 15
>
> interrupt-names:
> - items:
> - - const: ccmpa0
> - - const: ccmpb0
> - - const: cmpc0
> - - const: cmpd0
> - - const: cmpe0
> - - const: cmpf0
> - - const: adtrga0
> - - const: adtrgb0
> - - const: ovf0
> - - const: unf0
> - - const: ccmpa1
> - - const: ccmpb1
> - - const: cmpc1
> - - const: cmpd1
> - - const: cmpe1
> - - const: cmpf1
> - - const: adtrga1
> - - const: adtrgb1
> - - const: ovf1
> - - const: unf1
> - - const: ccmpa2
> - - const: ccmpb2
> - - const: cmpc2
> - - const: cmpd2
> - - const: cmpe2
> - - const: cmpf2
> - - const: adtrga2
> - - const: adtrgb2
> - - const: ovf2
> - - const: unf2
> - - const: ccmpa3
> - - const: ccmpb3
> - - const: cmpc3
> - - const: cmpd3
> - - const: cmpe3
> - - const: cmpf3
> - - const: adtrga3
> - - const: adtrgb3
> - - const: ovf3
> - - const: unf3
> - - const: ccmpa4
> - - const: ccmpb4
> - - const: cmpc4
> - - const: cmpd4
> - - const: cmpe4
> - - const: cmpf4
> - - const: adtrga4
> - - const: adtrgb4
> - - const: ovf4
> - - const: unf4
> - - const: ccmpa5
> - - const: ccmpb5
> - - const: cmpc5
> - - const: cmpd5
> - - const: cmpe5
> - - const: cmpf5
> - - const: adtrga5
> - - const: adtrgb5
> - - const: ovf5
> - - const: unf5
> - - const: ccmpa6
> - - const: ccmpb6
> - - const: cmpc6
> - - const: cmpd6
> - - const: cmpe6
> - - const: cmpf6
> - - const: adtrga6
> - - const: adtrgb6
> - - const: ovf6
> - - const: unf6
> - - const: ccmpa7
> - - const: ccmpb7
> - - const: cmpc7
> - - const: cmpd7
> - - const: cmpe7
> - - const: cmpf7
> - - const: adtrga7
> - - const: adtrgb7
> - - const: ovf7
> - - const: unf7
> + oneOf:
> + - items:
> + - const: ccmpa0
> + - const: ccmpb0
> + - const: cmpc0
> + - const: cmpd0
> + - const: cmpe0
> + - const: cmpf0
> + - const: adtrga0
> + - const: adtrgb0
> + - const: ovf0
> + - const: unf0
> + - const: ccmpa1
> + - const: ccmpb1
> + - const: cmpc1
> + - const: cmpd1
> + - const: cmpe1
> + - const: cmpf1
> + - const: adtrga1
> + - const: adtrgb1
> + - const: ovf1
> + - const: unf1
> + - const: ccmpa2
> + - const: ccmpb2
> + - const: cmpc2
> + - const: cmpd2
> + - const: cmpe2
> + - const: cmpf2
> + - const: adtrga2
> + - const: adtrgb2
> + - const: ovf2
> + - const: unf2
> + - const: ccmpa3
> + - const: ccmpb3
> + - const: cmpc3
> + - const: cmpd3
> + - const: cmpe3
> + - const: cmpf3
> + - const: adtrga3
> + - const: adtrgb3
> + - const: ovf3
> + - const: unf3
> + - const: ccmpa4
> + - const: ccmpb4
> + - const: cmpc4
> + - const: cmpd4
> + - const: cmpe4
> + - const: cmpf4
> + - const: adtrga4
> + - const: adtrgb4
> + - const: ovf4
> + - const: unf4
> + - const: ccmpa5
> + - const: ccmpb5
> + - const: cmpc5
> + - const: cmpd5
> + - const: cmpe5
> + - const: cmpf5
> + - const: adtrga5
> + - const: adtrgb5
> + - const: ovf5
> + - const: unf5
> + - const: ccmpa6
> + - const: ccmpb6
> + - const: cmpc6
> + - const: cmpd6
> + - const: cmpe6
> + - const: cmpf6
> + - const: adtrga6
> + - const: adtrgb6
> + - const: ovf6
> + - const: unf6
> + - const: ccmpa7
> + - const: ccmpb7
> + - const: cmpc7
> + - const: cmpd7
> + - const: cmpe7
> + - const: cmpf7
> + - const: adtrga7
> + - const: adtrgb7
> + - const: ovf7
> + - const: unf7
> + - items:
> + - const: gtcia0
> + - const: gtcib0
> + - const: gtcic0
> + - const: gtcid0
> + - const: gtcie0
> + - const: gtcif0
> + - const: gtcih0
> + - const: gtcil0
> + - const: gtcia1
> + - const: gtcib1
> + - const: gtcic1
> + - const: gtcid1
> + - const: gtcie1
> + - const: gtcif1
> + - const: gtcih1
> + - const: gtcil1
> + - const: gtcia2
> + - const: gtcib2
> + - const: gtcic2
> + - const: gtcid2
> + - const: gtcie2
> + - const: gtcif2
> + - const: gtcih2
> + - const: gtcil2
> + - const: gtcia3
> + - const: gtcib3
> + - const: gtcic3
> + - const: gtcid3
> + - const: gtcie3
> + - const: gtcif3
> + - const: gtcih3
> + - const: gtcil3
> + - const: gtcia4
> + - const: gtcib4
> + - const: gtcic4
> + - const: gtcid4
> + - const: gtcie4
> + - const: gtcif4
> + - const: gtcih4
> + - const: gtcil4
> + - const: gtcia5
> + - const: gtcib5
> + - const: gtcic5
> + - const: gtcid5
> + - const: gtcie5
> + - const: gtcif5
> + - const: gtcih5
> + - const: gtcil5
> + - const: gtcia6
> + - const: gtcib6
> + - const: gtcic6
> + - const: gtcid6
> + - const: gtcie6
> + - const: gtcif6
> + - const: gtcih6
> + - const: gtcil6
> + - const: gtcia7
> + - const: gtcib7
> + - const: gtcic7
> + - const: gtcid7
> + - const: gtcie7
> + - const: gtcif7
> + - const: gtcih7
> + - const: gtcil7
>
> clocks:
> - maxItems: 1
> + items:
> + - description: Core clock (PCLKD)
> + - description: Bus clock (PCLKA)
> + minItems: 1
> +
> + clock-names:
> + items:
> + - const: core
> + - const: bus
>
> power-domains:
> maxItems: 1
>
> resets:
> - maxItems: 1
> + items:
> + - description: Reset for bus clock (PCLKA/PCLKD)
> + - description: Reset for core clock (PCLKD)
> + minItems: 1
> +
> + reset-names:
> + items:
> + - const: rst_p
> + - const: rst_s
>
> required:
> - compatible
> @@ -257,6 +408,42 @@ required:
> allOf:
> - $ref: pwm.yaml#
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g047-gpt
> + then:
> + properties:
> + clocks:
> + minItems: 2
> + resets:
> + minItems: 2
> + interrupts:
> + maxItems: 64
> + interrupt-names:
> + maxItems: 64
> +
> + required:
> + - clock-names
> + - reset-names
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,rzg2l-gpt
> + then:
> + properties:
> + clocks:
> + maxItems: 1
> + resets:
> + maxItems: 1
> + interrupts:
> + minItems: 80
> + interrupt-names:
> + minItems: 80
> +
> additionalProperties: false
>
> examples:
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 6/7] arm64: dts: renesas: r9a09g047: Add GPT nodes
2025-08-14 18:41 ` [PATCH 6/7] arm64: dts: renesas: r9a09g047: Add GPT nodes Biju
@ 2025-08-19 16:24 ` Tommaso Merciai
0 siblings, 0 replies; 9+ messages in thread
From: Tommaso Merciai @ 2025-08-19 16:24 UTC (permalink / raw)
To: Biju
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Biju Das, linux-renesas-soc, devicetree,
linux-kernel, Prabhakar Mahadev Lad
Hi Biju,
Thank you for your patch.
On Thu, Aug 14, 2025 at 07:41:10PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The RZ/G3E SoC has 2 GPT's. Add GPT nodes to RZ/G3E ("R9A09G047") SoC
> DTSI.
>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 184 +++++++++++++++++++++
> 1 file changed, 184 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> index eeccd1345f71..0e6867ad112a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -552,6 +552,190 @@ channel5 {
> };
> };
>
> + gpt0: pwm@13010000 {
> + compatible = "renesas,r9a09g047-gpt";
> + reg = <0 0x13010000 0 0x10000>;
> + #pwm-cells = <3>;
> + interrupts = <GIC_SPI 538 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 554 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 562 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 586 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 594 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 539 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 555 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 563 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 579 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 540 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 548 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 556 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 572 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 580 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 541 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 549 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 557 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 573 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 581 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 589 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 597 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 542 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 550 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 558 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 566 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 582 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 590 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 598 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 543 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 551 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 559 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 567 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 575 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 544 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 552 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 560 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 584 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 553 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 561 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 577 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 593 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
> + "gtcie0", "gtcif0", "gtcih0", "gtcil0",
> + "gtcia1", "gtcib1", "gtcic1", "gtcid1",
> + "gtcie1", "gtcif1", "gtcih1", "gtcil1",
> + "gtcia2", "gtcib2", "gtcic2", "gtcid2",
> + "gtcie2", "gtcif2", "gtcih2", "gtcil2",
> + "gtcia3", "gtcib3", "gtcic3", "gtcid3",
> + "gtcie3", "gtcif3", "gtcih3", "gtcil3",
> + "gtcia4", "gtcib4", "gtcic4", "gtcid4",
> + "gtcie4", "gtcif4", "gtcih4", "gtcil4",
> + "gtcia5", "gtcib5", "gtcic5", "gtcid5",
> + "gtcie5", "gtcif5", "gtcih5", "gtcil5",
> + "gtcia6", "gtcib6", "gtcic6", "gtcid6",
> + "gtcie6", "gtcif6", "gtcih6", "gtcil6",
> + "gtcia7", "gtcib7", "gtcic7", "gtcid7",
> + "gtcie7", "gtcif7", "gtcih7", "gtcil7";
> + clocks = <&cpg CPG_CORE R9A09G047_GPT_0_CLKS_GPT>, <&cpg CPG_MOD 0x31>;
> + clock-names = "core", "bus";
> + resets = <&cpg 0x59>, <&cpg 0x5a>;
> + reset-names = "rst_p", "rst_s";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> + gpt1: pwm@13020000 {
> + compatible = "renesas,r9a09g047-gpt";
> + reg = <0 0x13020000 0 0x10000>;
> + #pwm-cells = <3>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 610 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 618 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 626 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 642 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 658 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 627 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 659 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 628 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 636 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 652 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 660 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 613 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 621 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 629 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 637 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 661 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 614 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 622 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 630 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 646 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 662 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 631 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 647 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 663 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 632 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 656 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 609 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 617 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 625 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 633 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 665 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
> + "gtcie0", "gtcif0", "gtcih0", "gtcil0",
> + "gtcia1", "gtcib1", "gtcic1", "gtcid1",
> + "gtcie1", "gtcif1", "gtcih1", "gtcil1",
> + "gtcia2", "gtcib2", "gtcic2", "gtcid2",
> + "gtcie2", "gtcif2", "gtcih2", "gtcil2",
> + "gtcia3", "gtcib3", "gtcic3", "gtcid3",
> + "gtcie3", "gtcif3", "gtcih3", "gtcil3",
> + "gtcia4", "gtcib4", "gtcic4", "gtcid4",
> + "gtcie4", "gtcif4", "gtcih4", "gtcil4",
> + "gtcia5", "gtcib5", "gtcic5", "gtcid5",
> + "gtcie5", "gtcif5", "gtcih5", "gtcil5",
> + "gtcia6", "gtcib6", "gtcic6", "gtcid6",
> + "gtcie6", "gtcif6", "gtcih6", "gtcil6",
> + "gtcia7", "gtcib7", "gtcic7", "gtcid7",
> + "gtcie7", "gtcif7", "gtcih7", "gtcil7";
> + clocks = <&cpg CPG_CORE R9A09G047_GPT_1_CLKS_GPT>, <&cpg CPG_MOD 0x32>;
> + clock-names = "core", "bus";
> + resets = <&cpg 0x5b>, <&cpg 0x5c>;
> + reset-names = "rst_p", "rst_s";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> wdt1: watchdog@14400000 {
> compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
> reg = <0 0x14400000 0 0x400>;
> --
> 2.43.0
>
Thanks & Regards,
Tommaso
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 7/7] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board
2025-08-14 18:41 ` [PATCH 7/7] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board Biju
@ 2025-08-19 16:25 ` Tommaso Merciai
0 siblings, 0 replies; 9+ messages in thread
From: Tommaso Merciai @ 2025-08-19 16:25 UTC (permalink / raw)
To: Biju
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Biju Das, linux-renesas-soc, devicetree,
linux-kernel, Prabhakar Mahadev Lad
Hi Biju,
Thank you for your patch.
On Thu, Aug 14, 2025 at 07:41:11PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The GTIOC4{A,B} IOs are available on the carrier board's PMOD1_6A
> connector. Enable the GPT on the carrier board by adding the GPT pinmux
> and node on the carrier board dtsi file.
>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> index 1e67f0a2a945..093c0202b4f9 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> @@ -84,6 +84,14 @@ &can_transceiver1 {
> };
> #endif
>
> +#if (!SW_LCD_EN) && (!SW_GPIO8_CAN0_STB)
> +&gpt0 {
> + pinctrl-0 = <&gpt0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +#endif
> +
> &i2c0 {
> pinctrl-0 = <&i2c0_pins>;
> pinctrl-names = "default";
> @@ -125,6 +133,11 @@ can4_pins: can4 {
> };
> };
>
> + gpt0_pins: gpt0 {
> + pinmux = <RZG3E_PORT_PINMUX(5, 4, 10)>, /* GTIOC4A */
> + <RZG3E_PORT_PINMUX(5, 5, 10)>; /* GTIOC4B */
> + };
> +
> i2c0_pins: i2c0 {
> pinmux = <RZG3E_PORT_PINMUX(D, 4, 4)>, /* SCL0 */
> <RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
> --
> 2.43.0
>
Thanks & Regards,
Tommaso
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
2025-08-19 16:18 ` Tommaso Merciai
@ 2025-08-20 20:29 ` Rob Herring
2025-08-21 7:04 ` Biju Das
1 sibling, 1 reply; 9+ messages in thread
From: Rob Herring @ 2025-08-20 20:29 UTC (permalink / raw)
To: Biju
Cc: Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Biju Das, linux-pwm, devicetree,
linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
On Thu, Aug 14, 2025 at 07:41:05PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
> SoC.
>
> The GPT IP on these parts is similar to that on RZ/G2L but supports
> only 8 interrupts per channel and has multiple clocks and resets.
> Introduce a new compatible string `renesas,r9a09g047-gpt` for RZ/G3E.
Doesn't look like a lot in common to me. I think this should be a
separate document.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 525 ++++++++++++------
> 1 file changed, 356 insertions(+), 169 deletions(-)
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
2025-08-20 20:29 ` Rob Herring
@ 2025-08-21 7:04 ` Biju Das
0 siblings, 0 replies; 9+ messages in thread
From: Biju Das @ 2025-08-21 7:04 UTC (permalink / raw)
To: Rob Herring, biju.das.au
Cc: Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, magnus.damm, linux-pwm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad
Hi Rob,
Thanks for the feedback.
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 20 August 2025 21:29
> Subject: Re: [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
>
> On Thu, Aug 14, 2025 at 07:41:05PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
> > SoC.
> >
> > The GPT IP on these parts is similar to that on RZ/G2L but supports
> > only 8 interrupts per channel and has multiple clocks and resets.
> > Introduce a new compatible string `renesas,r9a09g047-gpt` for RZ/G3E.
>
> Doesn't look like a lot in common to me. I think this should be a separate document.
OK, I will describe it in a separate document.
Cheers,
Biju
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-08-21 7:04 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
2025-08-19 16:18 ` Tommaso Merciai
2025-08-20 20:29 ` Rob Herring
2025-08-21 7:04 ` Biju Das
2025-08-14 18:41 ` [PATCH 6/7] arm64: dts: renesas: r9a09g047: Add GPT nodes Biju
2025-08-19 16:24 ` Tommaso Merciai
2025-08-14 18:41 ` [PATCH 7/7] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board Biju
2025-08-19 16:25 ` Tommaso Merciai
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