From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFF57279DD3; Thu, 14 Aug 2025 22:04:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755209085; cv=none; b=M5wkEMhf3lC7EyQqH0Q9mFwDTJp910HMGkq8wpSI4gmGcOo6tqsOMAfJtk2WbEYPBBuzwth0tIA6sLXIpDzgs2162jLKCaIeSq2RTKyS4GCm6c3tHPZMdsHvtyZFAj4egk3FzPJYeqLf98/aIjoFOCr41skjsMWHU2eNhWnb43s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755209085; c=relaxed/simple; bh=gHu78kUOor8hxYgQbCL2CU5u8RDiVxrUTQKMzNK+XDw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=GjJ727Lxf7+U1Kti0daMWRg9kiGI1jlR2MSOH+Zy1SXcKto4rM3BqVU+PMfRkDBYJhD3lYgcJI8gxhurP0AksyQmhyg+8Nr5tQ+rsIJkZx5dpmACzNOEtpCrate8+PP1/L8hpUZUgQHjwhkWeYUNje5P9ur5A3pOzR3ccOuqSLM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g8/5OuAD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g8/5OuAD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31BE0C4CEED; Thu, 14 Aug 2025 22:04:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755209085; bh=gHu78kUOor8hxYgQbCL2CU5u8RDiVxrUTQKMzNK+XDw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=g8/5OuADXwVKBkCbfeV0TU4cs5i6vUp0l+zU4dWyEGqaVUQYAkqc9vSxTBvkEtCGD XF2CEfdZ+q3dBPIabPAU0Kkn4zgUW/D9BmTKTj30iDL24MJX1T6XyoHfHW9tsvIJPD CqyQ5qgTZ7q1Xk74I2jYRy8QpfoAPmAL6UTvXxsIZzF8KH4HuMzBCDbbq+e2/bujYh l6qQ1FNqioSQkdZCxLYz6G8H68Fv9TMrrZ8EBdJpycyadg9st04G4Ygu2ShEo1xRF3 liSKFljiXhGhIzGljseTUa4YIePXyBzds3AUg8AWkd7OvxDY3XnFG6L7UWWzkFbPCx Q1FgPeg3xihZw== Date: Thu, 14 Aug 2025 17:04:44 -0500 From: Rob Herring To: Icenowy Zheng Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski , Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [RFC PATCH 2/8] dt-bindings: display: add versilicon,dc Message-ID: <20250814220444.GA3988176-robh@kernel.org> References: <20250814164048.2336043-1-uwu@icenowy.me> <20250814164048.2336043-3-uwu@icenowy.me> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250814164048.2336043-3-uwu@icenowy.me> On Fri, Aug 15, 2025 at 12:40:42AM +0800, Icenowy Zheng wrote: > Verisilicon has a series of display controllers prefixed with DC and > with self-identification facility like their GC series GPUs. > > Add a device tree binding for it. > > Depends on the specific DC model, it can have either one or two display > outputs, and each display output could be set to DPI signal or "DP" > signal (which seems to be some plain parallel bus to HDMI controllers). > > Signed-off-by: Icenowy Zheng > --- > .../bindings/display/verisilicon,dc.yaml | 127 ++++++++++++++++++ > 1 file changed, 127 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > new file mode 100644 > index 0000000000000..2f71a811786aa > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > @@ -0,0 +1,127 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Verisilicon DC-series display controllers > + > +maintainers: > + - Icenowy Zheng > + > +properties: > + $nodename: > + pattern: "^display@[0-9a-f]+$" > + > + compatible: > + const: verisilicon,dc If the clocks or resets varies by platform, then you need an SoC specific compatible still. If these clocks/resets are straight from the RTL and any other number of clocks/resets is wrong, then we can stick with just this compatible. > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: DC Core clock > + - description: DMA AXI bus clock > + - description: Configuration AHB bus clock > + - description: Pixel clock of output 0 > + - description: Pixel clock of output 1 > + minItems: 4 Generally we put this before 'items'. > + > + clock-names: > + items: > + - const: core > + - const: axi > + - const: ahb > + - const: pix0 > + - const: pix1 > + minItems: 4 > + > + resets: > + items: > + - description: DC Core reset > + - description: DMA AXI bus reset > + - description: Configuration AHB bus reset > + > + reset-names: > + items: > + - const: core > + - const: axi > + - const: ahb > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: The first output channel, endpoint 0 should be > + used for DPI format output and endpoint 1 should be used > + for DP format output. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: The second output channel if the DC variant > + supports and used. Follow the same endpoint addressing > + rule with the first port. > + > + required: > + - port@0 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + display@ffef600000 { > + compatible = "verisilicon,dc"; > + reg = <0xff 0xef600000 0x0 0x100000>; > + interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk_vo CLK_DPU_CCLK>, > + <&clk_vo CLK_DPU_ACLK>, > + <&clk_vo CLK_DPU_HCLK>, > + <&clk_vo CLK_DPU_PIXELCLK0>, > + <&clk_vo CLK_DPU_PIXELCLK1>; > + clock-names = "core", "axi", "ahb", "pix0", "pix1"; > + resets = <&rst TH1520_RESET_ID_DPU_CORE>, > + <&rst TH1520_RESET_ID_DPU_AXI>, > + <&rst TH1520_RESET_ID_DPU_AHB>; > + reset-names = "core", "axi", "ahb"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + }; > + > + port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + dpu_out_dp1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&hdmi_in>; > + }; > + }; > + }; > + }; > + }; > -- > 2.50.1 >