From: Aaron Kling via B4 Relay <devnull+webgeek1234.gmail.com@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Joseph Lo <josephl@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
Thierry Reding <treding@nvidia.com>,
Aaron Kling <webgeek1234@gmail.com>
Subject: [PATCH 1/5] dt-bindings: clock: tegra124-dfll: Add property to limit frequency
Date: Sat, 16 Aug 2025 00:53:33 -0500 [thread overview]
Message-ID: <20250816-tegra210-speedo-v1-1-a981360adc27@gmail.com> (raw)
In-Reply-To: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com>
From: Aaron Kling <webgeek1234@gmail.com>
Some devices report a cpu speedo value that corresponds to a table that
scales beyond the chips capability. This allows devices to set a lower
limit.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
index f7d347385b5775ddd702ecbb9821acfc9d4b9ff2..6cdbabc1f036a767bdc8e5df64eeff34171a3b85 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
@@ -70,6 +70,9 @@ Required properties for PWM mode:
- dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
- dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
+Optional properties for limiting frequency:
+- nvidia,dfll-max-freq: Maximum scaling frequency.
+
Example for I2C:
clock@70110000 {
--
2.50.1
next prev parent reply other threads:[~2025-08-16 5:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-16 5:53 [PATCH 0/5] Properly Limit Tegra210 Clock Rates Aaron Kling via B4 Relay
2025-08-16 5:53 ` Aaron Kling via B4 Relay [this message]
2025-08-16 8:21 ` [PATCH 1/5] dt-bindings: clock: tegra124-dfll: Add property to limit frequency Krzysztof Kozlowski
2025-08-18 3:23 ` Aaron Kling
2025-08-18 6:31 ` Krzysztof Kozlowski
2025-08-16 5:53 ` [PATCH 2/5] soc: tegra: fuse: speedo-tegra210: Update speedo ids Aaron Kling via B4 Relay
2025-09-03 6:39 ` Mikko Perttunen
2025-08-16 5:53 ` [PATCH 3/5] soc: tegra: fuse: speedo-tegra210: Add sku 0x8F Aaron Kling via B4 Relay
2025-08-16 5:53 ` [PATCH 4/5] clk: tegra: dfll: Support limiting max clock per device Aaron Kling via B4 Relay
2025-08-16 5:53 ` [PATCH 5/5] arm64: tegra: Limit max cpu frequency on P3450 Aaron Kling via B4 Relay
2025-09-03 5:50 ` Mikko Perttunen
2025-09-03 6:28 ` Aaron Kling
2025-09-03 7:29 ` Mikko Perttunen
2025-09-03 8:01 ` Aaron Kling
2025-09-04 0:55 ` Mikko Perttunen
2025-09-04 1:55 ` Aaron Kling
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