From: Aaron Kling via B4 Relay <devnull+webgeek1234.gmail.com@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Joseph Lo <josephl@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
Thierry Reding <treding@nvidia.com>,
Aaron Kling <webgeek1234@gmail.com>
Subject: [PATCH 2/5] soc: tegra: fuse: speedo-tegra210: Update speedo ids
Date: Sat, 16 Aug 2025 00:53:34 -0500 [thread overview]
Message-ID: <20250816-tegra210-speedo-v1-2-a981360adc27@gmail.com> (raw)
In-Reply-To: <20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com>
From: Aaron Kling <webgeek1234@gmail.com>
Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs
code supports 11 ids and nouveau supports 5. This aligns with what the
downstream vendor kernel supports. Align the existing supported skus
with the downstream speedo list.
The Tegra210 CVB tables were added in the referenced fixes commit. Since
then, all Tegra210 socs have tried to scale to 1.9 GHz, when the
supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
Overclocking should not be the default state.
Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
drivers/soc/tegra/fuse/speedo-tegra210.c | 31 ++++++++++++++++++++++++-------
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/fuse/speedo-tegra210.c
index 695d0b7f9a8abe53c497155603147420cda40b63..909fdf8fcc9d9f5ac936ae322e7a73dc720e5ab6 100644
--- a/drivers/soc/tegra/fuse/speedo-tegra210.c
+++ b/drivers/soc/tegra/fuse/speedo-tegra210.c
@@ -68,18 +68,35 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
switch (sku) {
case 0x00: /* Engineering SKU */
case 0x01: /* Engineering SKU */
+ case 0x13:
+ if (speedo_rev >= 2) {
+ sku_info->cpu_speedo_id = 5;
+ sku_info->gpu_speedo_id = 2;
+ break;
+ }
+
+ sku_info->gpu_speedo_id = 1;
+ break;
+
case 0x07:
case 0x17:
- case 0x27:
- if (speedo_rev >= 2)
- sku_info->gpu_speedo_id = 1;
+ if (speedo_rev >= 2) {
+ sku_info->cpu_speedo_id = 7;
+ sku_info->gpu_speedo_id = 2;
+ break;
+ }
+
+ sku_info->gpu_speedo_id = 1;
break;
- case 0x13:
- if (speedo_rev >= 2)
- sku_info->gpu_speedo_id = 1;
+ case 0x27:
+ if (speedo_rev >= 2) {
+ sku_info->cpu_speedo_id = 1;
+ sku_info->gpu_speedo_id = 2;
+ break;
+ }
- sku_info->cpu_speedo_id = 1;
+ sku_info->gpu_speedo_id = 1;
break;
default:
--
2.50.1
next prev parent reply other threads:[~2025-08-16 5:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-16 5:53 [PATCH 0/5] Properly Limit Tegra210 Clock Rates Aaron Kling via B4 Relay
2025-08-16 5:53 ` [PATCH 1/5] dt-bindings: clock: tegra124-dfll: Add property to limit frequency Aaron Kling via B4 Relay
2025-08-16 8:21 ` Krzysztof Kozlowski
2025-08-18 3:23 ` Aaron Kling
2025-08-18 6:31 ` Krzysztof Kozlowski
2025-08-16 5:53 ` Aaron Kling via B4 Relay [this message]
2025-09-03 6:39 ` [PATCH 2/5] soc: tegra: fuse: speedo-tegra210: Update speedo ids Mikko Perttunen
2025-08-16 5:53 ` [PATCH 3/5] soc: tegra: fuse: speedo-tegra210: Add sku 0x8F Aaron Kling via B4 Relay
2025-08-16 5:53 ` [PATCH 4/5] clk: tegra: dfll: Support limiting max clock per device Aaron Kling via B4 Relay
2025-08-16 5:53 ` [PATCH 5/5] arm64: tegra: Limit max cpu frequency on P3450 Aaron Kling via B4 Relay
2025-09-03 5:50 ` Mikko Perttunen
2025-09-03 6:28 ` Aaron Kling
2025-09-03 7:29 ` Mikko Perttunen
2025-09-03 8:01 ` Aaron Kling
2025-09-04 0:55 ` Mikko Perttunen
2025-09-04 1:55 ` Aaron Kling
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250816-tegra210-speedo-v1-2-a981360adc27@gmail.com \
--to=devnull+webgeek1234.gmail.com@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jonathanh@nvidia.com \
--cc=josephl@nvidia.com \
--cc=krzk+dt@kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=pdeschrijver@nvidia.com \
--cc=pgaikwad@nvidia.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=thierry.reding@gmail.com \
--cc=treding@nvidia.com \
--cc=webgeek1234@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).