From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F24B31A061; Tue, 19 Aug 2025 09:18:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755595140; cv=none; b=W1KN32opDn+dE3Fk/+QpzuNjDh2ed5F8FLewFryXSiNUOe7XMgrqJZ03BfDKJQT23j2IxlOYMsUBaB+1uPLZ6xRewfH9SgAjAVQP3CbcHHMz8AUp+7uh93Uz0YVNaqWiK0FwMN95kbMNds3/dnIvnxL1RA2FCKu27ikki5hQNmE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755595140; c=relaxed/simple; bh=OYdOTPp/WleG/23x+u2iGWLmZo8oqF7YKe5sSXtY4gI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Wn3MtYqajp4jNIEmaF1l4uAIg64x0dOsKvfNj4L2uLI2qbF1jMqFTVjY5PvAVHDvSsMLy3TbxKF+4YrzTaxfLEfBXisf3EH2WssU0GbQtzG9HbKdaHg8H3/JnE30l2OuKOGeps7sine+W2CyHV3EgwjkTjxLY6p0REwRqwku7bU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=wLEfmWRc; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="wLEfmWRc" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J93bvK024068; Tue, 19 Aug 2025 11:18:30 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= kyXtN74VkBaQLErnP6Oirfq2yZX1obNwJfBjqV4IEtw=; b=wLEfmWRcpN/2fSsL 0p9nN+Bozh9PyYXVAGIp2580Wqkx1dJ+eld5kcWViuPbHTLUSqahv/huKW5+tuZ/ pmicCG3sDCXqLMX1vAHuY+eN+JVWQOh7Owx7pXIRtiMIwa5+aiBeQTu6UOMmyMKQ wHPYRIFrBzaIa8vPraO6aKFNmrtID/j7ui0lNeaP+hmpfalrQ0MDGkcUHL2/hPtB wpt8kyJNAef+3mFNajB0NF1Th8EYVPDQgdlnyG8C8WmW2nfz+BZHYMpDO5oCX01M 1Yf1vQupfQk9a+XyAMjzlfjNUUaVZSa6nuZpEHZ7bGNNL6M7Br0wHUkyMSsZDJis 2fS12A== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48jhb1t8py-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Aug 2025 11:18:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5584F40053; Tue, 19 Aug 2025 11:16:58 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 98F3371763B; Tue, 19 Aug 2025 11:16:00 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:16:00 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:15:59 +0200 Subject: [PATCH v3 06/13] dt-bindings: arm: stm32: add required #clock-cells property Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250819-drm-misc-next-v3-6-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 On STM32MP25 SoC, the syscfg peripheral provides a clock to the display subsystem through a multiplexer. Since it only provides a single clock, the cell value is 0. Doing so allows the clock consumers to reach the peripheral and gate the clock accordingly. Reviewed-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 31 +++++++++++++++------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ed97652c84922813e94b1818c07fe8714891c089..95d2319afe235fa86974d80f89c9deeae2275232 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -36,20 +36,31 @@ properties: clocks: maxItems: 1 + "#clock-cells": + const: 0 + required: - compatible - reg -if: - properties: - compatible: - contains: - enum: - - st,stm32mp157-syscfg - - st,stm32f4-gcan -then: - required: - - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg + - st,stm32f4-gcan + then: + required: + - clocks + - if: + properties: + compatible: + const: st,stm32mp25-syscfg + then: + required: + - "#clock-cells" additionalProperties: false -- 2.25.1