From: Krzysztof Kozlowski <krzk@kernel.org>
To: E Shattow <e@freeshell.de>
Cc: Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Hal Feng <hal.feng@starfivetech.com>,
Minda Chen <minda.chen@starfivetech.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
Date: Tue, 19 Aug 2025 10:59:21 +0200 [thread overview]
Message-ID: <20250819-roaring-mutant-fox-a05caf@kuoka> (raw)
In-Reply-To: <20250815073739.79241-2-e@freeshell.de>
On Fri, Aug 15, 2025 at 12:37:21AM -0700, E Shattow wrote:
> +
> +title: StarFive JH7110 DMC
> +
> +maintainers:
> + - E Shattow <e@freeshell.de>
> +
> +description:
> + JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at 2133Mbps (up to 2800Mbps).
Please wrap at 80 (see Linux Coding style)
> +
> +properties:
> + compatible:
> + items:
> + - const: starfive,jh7110-dmc
> +
> + reg:
> + items:
> + - description: controller registers
> + - description: phy registers
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: pll1_out
pll
(this is name of input, not name of clock)
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-08-19 8:59 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-15 7:37 [PATCH v2 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow
2025-08-15 7:37 ` [PATCH v2 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC E Shattow
2025-08-19 8:59 ` Krzysztof Kozlowski [this message]
2025-08-15 7:37 ` [PATCH v2 2/3] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow
2025-08-18 6:23 ` Hal Feng
2025-08-15 7:37 ` [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow
2025-08-18 6:05 ` Hal Feng
2025-08-20 3:49 ` E Shattow
2025-08-22 9:27 ` Hal Feng
2025-08-23 8:10 ` E Shattow
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