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bh=FoPVuBStBvUM57EnDHdyDOSI/MqVu22rPsFJ0LZ4BLU=; b=MTv/99UW8etAyy5/38QR+E2c+ZruaERBMxdoqgEreTKCTZ09U1lN343bk9qUCYH2PBx3GVug3n5QHkIUu2u3e0nclzcRkZkJIePFH+KjzD3aPGg6GUAfG4Ae521HDkvmYOc1kXcWUWr3mSf45kMXm0/1zsj5OvRc+5JPJxWUAvg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=ariel.dalessandro@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1755710085; s=zohomail; d=collabora.com; i=ariel.dalessandro@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=FoPVuBStBvUM57EnDHdyDOSI/MqVu22rPsFJ0LZ4BLU=; b=jGjcsFSKI9tNIT2mMc7ULHhV9VXmZ2mN8VTO4r4iatqo2USNHECT9uTRPAvRboVX 7dseJNDMWoP6p5FI3rov+csDBr/HAyoSmH/HydhHOxtDjdVGeJsO8eo/iVBltpuH39e z9+rZe8b9K7VCyyS4CvyFRyVSsAyIU0yJ/VhAeIA= Received: by mx.zohomail.com with SMTPS id 1755710083545671.3749174712098; Wed, 20 Aug 2025 10:14:43 -0700 (PDT) From: Ariel D'Alessandro To: airlied@gmail.com, amergnat@baylibre.com, andrew+netdev@lunn.ch, andrew-ct.chen@mediatek.com, angelogioacchino.delregno@collabora.com, ariel.dalessandro@collabora.com, broonie@kernel.org, chunkuang.hu@kernel.org, ck.hu@mediatek.com, conor+dt@kernel.org, davem@davemloft.net, dmitry.torokhov@gmail.com, edumazet@google.com, flora.fu@mediatek.com, houlong.wei@mediatek.com, jeesw@melfas.com, jmassot@collabora.com, kernel@collabora.com, krzk+dt@kernel.org, kuba@kernel.org, kyrie.wu@mediatek.corp-partner.google.com, lgirdwood@gmail.com, linus.walleij@linaro.org, louisalexis.eyraud@collabora.com, maarten.lankhorst@linux.intel.com, matthias.bgg@gmail.com, mchehab@kernel.org, minghsiu.tsai@mediatek.com, mripard@kernel.org, p.zabel@pengutronix.de, pabeni@redhat.com, robh@kernel.org, sean.wang@kernel.org, simona@ffwll.ch, support.opensource@diasemi.com, tiffany.lin@mediatek.com, tzimmermann@suse.de, yunfei.dong@mediatek.com Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-input@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-sound@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v1 03/14] dt-bindings: arm: mediatek: mmsys: Add assigned-clocks/rates properties Date: Wed, 20 Aug 2025 14:12:51 -0300 Message-ID: <20250820171302.324142-4-ariel.dalessandro@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250820171302.324142-1-ariel.dalessandro@collabora.com> References: <20250820171302.324142-1-ariel.dalessandro@collabora.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-ZohoMailClient: External Current, the DT bindings for MediaTek mmsys controller is missing the assigned-clocks and assigned-clocks-rates properties. Add these and update the example as well. Signed-off-by: Ariel D'Alessandro --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 3f4262e93c789..d045d366eb8e2 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -68,6 +68,12 @@ properties: of the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for details. + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + mboxes: description: Using mailbox to communicate with GCE, it should have this @@ -130,6 +136,7 @@ additionalProperties: false examples: - | + #include #include #include @@ -137,6 +144,8 @@ examples: compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; + assigned-clock-rates = <400000000>; #clock-cells = <1>; #reset-cells = <1>; mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, -- 2.50.1