[PATCH] riscv: dts: spacemit: add UART resets for Soc K1

[PATCH] riscv: dts: spacemit: add UART resets for Soc K1

[Hendrik Hamerlinck]

Add reset control entries for all UARTs in the SpaceMIT K1 SoC Device Tree.
UART0 was functional as it did not need a reset. But the other UARTs were
unable to access their registers without the reset being applied.

Although perhaps not needed I did add the reset for UART0 as well,
to ensure consistency across all UARTs. With the current-speed set to
112500 baud rate, it matches the factory U-Boot settings.
This should not give issues with early console usage. But perhaps it could
be a good idea to let somebody else confirm this as well.

Tested this locally on both Orange Pi RV2 and Banana Pi BPI-F3 boards. 
I enabled the UART9 and was able to use it successfully.

Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be>
---
 arch/riscv/boot/dts/spacemit/k1.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index abde8bb07c95..7a5196a98085 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -667,6 +667,8 @@ uart0: serial@d4017000 {
 				clocks = <&syscon_apbc CLK_UART0>,
 					 <&syscon_apbc CLK_UART0_BUS>;
 				clock-names = "core", "bus";
+				current-speed = <115200>;
+				resets = <&syscon_apbc RESET_UART0>;
 				interrupts = <42>;
 				reg-shift = <2>;
 				reg-io-width = <4>;
@@ -680,6 +682,7 @@ uart2: serial@d4017100 {
 				clocks = <&syscon_apbc CLK_UART2>,
 					 <&syscon_apbc CLK_UART2_BUS>;
 				clock-names = "core", "bus";
+				resets = <&syscon_apbc RESET_UART2>;
 				interrupts = <44>;
 				reg-shift = <2>;
 				reg-io-width = <4>;
@@ -693,6 +696,7 @@ uart3: serial@d4017200 {
 				clocks = <&syscon_apbc CLK_UART3>,
 					 <&syscon_apbc CLK_UART3_BUS>;
 				clock-names = "core", "bus";
+				resets = <&syscon_apbc RESET_UART3>;
 				interrupts = <45>;
 				reg-shift = <2>;
 				reg-io-width = <4>;
@@ -706,6 +710,7 @@ uart4: serial@d4017300 {
 				clocks = <&syscon_apbc CLK_UART4>,
 					 <&syscon_apbc CLK_UART4_BUS>;
 				clock-names = "core", "bus";
+				resets = <&syscon_apbc RESET_UART4>;
 				interrupts = <46>;
 				reg-shift = <2>;
 				reg-io-width = <4>;
@@ -719,6 +724,7 @@ uart5: serial@d4017400 {
 				clocks = <&syscon_apbc CLK_UART5>,
 					 <&syscon_apbc CLK_UART5_BUS>;
 				clock-names = "core", "bus";
+				resets = <&syscon_apbc RESET_UART5>;
 				interrupts = <47>;
 				reg-shift = <2>;
 				reg-io-width = <4>;
@@ -732,6 +738,7 @@ uart6: serial@d4017500 {
 				clocks = <&syscon_apbc CLK_UART6>,
 					 <&syscon_apbc CLK_UART6_BUS>;
 				clock-names = "core", "bus";
+				resets = <&syscon_apbc RESET_UART6>;
 				interrupts = <48>;
 				reg-shift = <2>;
 				reg-io-width = <4>;
@@ -745,6 +752,7 @@ uart7: serial@d4017600 {
 				clocks = <&syscon_apbc CLK_UART7>,
 					 <&syscon_apbc CLK_UART7_BUS>;
 				clock-names = "core", "bus";
+				resets = <&syscon_apbc RESET_UART7>;
 				interrupts = <49>;
 				reg-shift = <2>;
 				reg-io-width = <4>;
@@ -758,6 +766,7 @@ uart8: serial@d4017700 {
 				clocks = <&syscon_apbc CLK_UART8>,
 					 <&syscon_apbc CLK_UART8_BUS>;
 				clock-names = "core", "bus";
+				resets = <&syscon_apbc RESET_UART8>;
 				interrupts = <50>;
 				reg-shift = <2>;
 				reg-io-width = <4>;
@@ -771,6 +780,7 @@ uart9: serial@d4017800 {
 				clocks = <&syscon_apbc CLK_UART9>,
 					 <&syscon_apbc CLK_UART9_BUS>;
 				clock-names = "core", "bus";
+				resets = <&syscon_apbc RESET_UART9>;
 				interrupts = <51>;
 				reg-shift = <2>;
 				reg-io-width = <4>;
-- 
2.43.0

Re: [PATCH] riscv: dts: spacemit: add UART resets for Soc K1

[Hendrik Hamerlinck]

Hello,

On 8/7/25 21:18, Hendrik Hamerlinck wrote:
> Add reset control entries for all UARTs in the SpaceMIT K1 SoC Device Tree.
> UART0 was functional as it did not need a reset. But the other UARTs were
> unable to access their registers without the reset being applied.
>
> Although perhaps not needed I did add the reset for UART0 as well,
> to ensure consistency across all UARTs. With the current-speed set to
> 112500 baud rate, it matches the factory U-Boot settings.
> This should not give issues with early console usage. But perhaps it could
> be a good idea to let somebody else confirm this as well.
I have tested this version for a while and no longer see the need for
additional confirmation.

>
> Tested this locally on both Orange Pi RV2 and Banana Pi BPI-F3 boards. 
> I enabled the UART9 and was able to use it successfully.
>
Just a gentle reminder about this patch.

All UARTs are listed in the K1 device tree and probed by the 8250_of driver,
but without reset lines most of them are non-functional. Adding the resets
makes them usable when mapped to devices.

This patch is limited to DTS reset handling, so UARTs are usable in the
current state. I’m aware Alex Elder is assigned to the UART peripheral on
the wiki and will likely handle the broader driver improvements (DMA,
clock updates, full baud-rate support), so this should not interfere with
that work.

Thanks for taking a look!

Kind regards,
Hendrik

Re: [PATCH] riscv: dts: spacemit: add UART resets for Soc K1

[Yixun Lan]

On 20:27 Wed 20 Aug     , Hendrik Hamerlinck wrote:
> Hello,
> 
> On 8/7/25 21:18, Hendrik Hamerlinck wrote:
> > Add reset control entries for all UARTs in the SpaceMIT K1 SoC Device Tree.
> > UART0 was functional as it did not need a reset. But the other UARTs were
> > unable to access their registers without the reset being applied.
> >
> > Although perhaps not needed I did add the reset for UART0 as well,
> > to ensure consistency across all UARTs. With the current-speed set to
> > 112500 baud rate, it matches the factory U-Boot settings.
> > This should not give issues with early console usage. But perhaps it could
> > be a good idea to let somebody else confirm this as well.
> I have tested this version for a while and no longer see the need for
> additional confirmation.
> 
> >
> > Tested this locally on both Orange Pi RV2 and Banana Pi BPI-F3 boards. 
> > I enabled the UART9 and was able to use it successfully.
> >
> Just a gentle reminder about this patch.
> 
> All UARTs are listed in the K1 device tree and probed by the 8250_of driver,
> but without reset lines most of them are non-functional. Adding the resets
> makes them usable when mapped to devices.
> 
that probably due to other UARTs are in assert mode by default, while
UART0 already configured by bootloader..

> This patch is limited to DTS reset handling, so UARTs are usable in the
> current state. I’m aware Alex Elder is assigned to the UART peripheral on
> the wiki and will likely handle the broader driver improvements (DMA,
> clock updates, full baud-rate support), so this should not interfere with
> that work.
> 
> Thanks for taking a look!
> 
> Kind regards,
> Hendrik
> 

-- 
Yixun Lan (dlan)

Re: [PATCH] riscv: dts: spacemit: add UART resets for Soc K1

[Yixun Lan]

Hi Hendrik, 

On 21:18 Thu 07 Aug     , Hendrik Hamerlinck wrote:
> Add reset control entries for all UARTs in the SpaceMIT K1 SoC Device Tree.
> UART0 was functional as it did not need a reset. But the other UARTs were
> unable to access their registers without the reset being applied.
> 
..
> Although perhaps not needed I did add the reset for UART0 as well,
> to ensure consistency across all UARTs. With the current-speed set to
> 112500 baud rate, it matches the factory U-Boot settings.
> This should not give issues with early console usage. But perhaps it could
> be a good idea to let somebody else confirm this as well.
> 
Adding reset to UART0 is just fine, so we don't need to presume it will
rely on bootloader to de-assert the controller

please write changelogs in imperative mood, you can follow
https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog

> Tested this locally on both Orange Pi RV2 and Banana Pi BPI-F3 boards. 
> I enabled the UART9 and was able to use it successfully.
> 
> Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be>
> ---
>  arch/riscv/boot/dts/spacemit/k1.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index abde8bb07c95..7a5196a98085 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -667,6 +667,8 @@ uart0: serial@d4017000 {
>  				clocks = <&syscon_apbc CLK_UART0>,
>  					 <&syscon_apbc CLK_UART0_BUS>;
>  				clock-names = "core", "bus";
..
> +				current-speed = <115200>;
please drop this property, dtsi file should contain generic info for SoC,
even in real cases, all boards use UART0 as serial output and configured
at baudrate 115200, it still be able to alter to different frequency..

besides, if you really want to set baudrate, then I'd suggest to configure
it at board specific dts file, 
  stdout-path = "serial0:115200n8";

> +				resets = <&syscon_apbc RESET_UART0>;
>  				interrupts = <42>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -680,6 +682,7 @@ uart2: serial@d4017100 {
>  				clocks = <&syscon_apbc CLK_UART2>,
>  					 <&syscon_apbc CLK_UART2_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART2>;
>  				interrupts = <44>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -693,6 +696,7 @@ uart3: serial@d4017200 {
>  				clocks = <&syscon_apbc CLK_UART3>,
>  					 <&syscon_apbc CLK_UART3_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART3>;
>  				interrupts = <45>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -706,6 +710,7 @@ uart4: serial@d4017300 {
>  				clocks = <&syscon_apbc CLK_UART4>,
>  					 <&syscon_apbc CLK_UART4_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART4>;
>  				interrupts = <46>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -719,6 +724,7 @@ uart5: serial@d4017400 {
>  				clocks = <&syscon_apbc CLK_UART5>,
>  					 <&syscon_apbc CLK_UART5_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART5>;
>  				interrupts = <47>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -732,6 +738,7 @@ uart6: serial@d4017500 {
>  				clocks = <&syscon_apbc CLK_UART6>,
>  					 <&syscon_apbc CLK_UART6_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART6>;
>  				interrupts = <48>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -745,6 +752,7 @@ uart7: serial@d4017600 {
>  				clocks = <&syscon_apbc CLK_UART7>,
>  					 <&syscon_apbc CLK_UART7_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART7>;
>  				interrupts = <49>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -758,6 +766,7 @@ uart8: serial@d4017700 {
>  				clocks = <&syscon_apbc CLK_UART8>,
>  					 <&syscon_apbc CLK_UART8_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART8>;
>  				interrupts = <50>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -771,6 +780,7 @@ uart9: serial@d4017800 {
>  				clocks = <&syscon_apbc CLK_UART9>,
>  					 <&syscon_apbc CLK_UART9_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART9>;
>  				interrupts = <51>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> -- 
> 2.43.0
> 

-- 
Yixun Lan (dlan)

Re: [PATCH] riscv: dts: spacemit: add UART resets for Soc K1

[Hendrik Hamerlinck]

Hello Yixun,

On 8/21/25 01:19, Yixun Lan wrote:
> Hi Hendrik, 
>
> On 21:18 Thu 07 Aug     , Hendrik Hamerlinck wrote:
>> Add reset control entries for all UARTs in the SpaceMIT K1 SoC Device Tree.
>> UART0 was functional as it did not need a reset. But the other UARTs were
>> unable to access their registers without the reset being applied.
>>
> ..
>> Although perhaps not needed I did add the reset for UART0 as well,
>> to ensure consistency across all UARTs. With the current-speed set to
>> 112500 baud rate, it matches the factory U-Boot settings.
>> This should not give issues with early console usage. But perhaps it could
>> be a good idea to let somebody else confirm this as well.
>>
> Adding reset to UART0 is just fine, so we don't need to presume it will
> rely on bootloader to de-assert the controller
>
> please write changelogs in imperative mood, you can follow
> https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog
Ok, I’ll update the changelog accordingly in v2.
>
>> Tested this locally on both Orange Pi RV2 and Banana Pi BPI-F3 boards. 
>> I enabled the UART9 and was able to use it successfully.
>>
>> Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be>
>> ---
>>  arch/riscv/boot/dts/spacemit/k1.dtsi | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
>> index abde8bb07c95..7a5196a98085 100644
>> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
>> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
>> @@ -667,6 +667,8 @@ uart0: serial@d4017000 {
>>  				clocks = <&syscon_apbc CLK_UART0>,
>>  					 <&syscon_apbc CLK_UART0_BUS>;
>>  				clock-names = "core", "bus";
> ..
>> +				current-speed = <115200>;
> please drop this property, dtsi file should contain generic info for SoC,
> even in real cases, all boards use UART0 as serial output and configured
> at baudrate 115200, it still be able to alter to different frequency..
>
> besides, if you really want to set baudrate, then I'd suggest to configure
> it at board specific dts file, 
>   stdout-path = "serial0:115200n8";
Understood, I’ll drop the `current-speed` property. It works without it.

Thanks for the review.

Kind regards,
Hendrik