From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D92930AAD2; Thu, 21 Aug 2025 11:12:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755774760; cv=none; b=b2wJow+n+fpI/IE4gH8CFaADcaXNvX1syOFx2AQaU3psD2YdLObTzirqQtKDXpPLcyVWMLCZSwR8jTcFDnpD2sbekTQHR7gERQUhjyqUY2UVdSC9B4r+OWSTfFgl8xx4w1ETq1YeNIKcrY30MJMIVAzzJNpW+BRNUj7qDlGig6w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755774760; c=relaxed/simple; bh=rGyJvKcya2Uu965KJpLUrN3i2ZDEqYn4LpHp20MPAlc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=rbrpHdjkhx3jKSKZLS2ch8bmk+rK8LTBFEKZmhOuZAaP7JsuOuLcl7YiNsbOrGtEmjlE5rISw53yKI6qWMyV+mQEG7+0S0HfAgyBp6VsLpKlwP3vuU58R0KnJxJknzzCDwhN4MZ61Znb5CQgQTPq7YKcoZOTIqDjYTLieuLIY7o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=SFTHTd7a; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="SFTHTd7a" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57LAT3k3011323; Thu, 21 Aug 2025 13:12:20 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= ssbplN6xP6Yb8xqVTeSdSuu1Z6zTfktHu8ETkXtqxKE=; b=SFTHTd7aZTeDlLSG J443NSeHX7DdxDZGisChXp0cAkxodKQRiaalMXgBOLhP2bwMRt+kKUQWhJlTxP+Y dWyp5dRHUJQBu0rc/3WJ9dUpvUClcgj+8CVIpKFz1wjUG1dw+JJXpXSS1Men0ysv hGQGiMpm1GTHz9beQDgj7wHro42mGuVLWisVsmqDmzNnvCohAyj2KU8M580hUkvs pYGOXcr9YT+W8jWzR07QUHhpi6ftcdD2xArUXHxbIO1X6BlxGV8nOe9TpC7CGKt+ xEL3ZmDyP5XL+dBbNeuBiU545pOJMVrFscUkQAftMsZDud67uVZR/EfKIoj0q2tf BU5ZnQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48n754ehje-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Aug 2025 13:12:20 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id B391540056; Thu, 21 Aug 2025 13:10:56 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 585C974EF0F; Thu, 21 Aug 2025 13:10:00 +0200 (CEST) Received: from localhost (10.252.7.99) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 21 Aug 2025 13:09:59 +0200 From: Raphael Gallais-Pou Date: Thu, 21 Aug 2025 13:09:00 +0200 Subject: [PATCH v4 10/13] arm64: dts: st: add ltdc support on stm32mp255 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250821-drm-misc-next-v4-10-7060500f8fd3@foss.st.com> References: <20250821-drm-misc-next-v4-0-7060500f8fd3@foss.st.com> In-Reply-To: <20250821-drm-misc-next-v4-0-7060500f8fd3@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-21_03,2025-08-20_03,2025-03-28_01 Add the LTDC node for stm32mp255 SoC and handle its loopback clocks. ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is semantically correct, it for now leads to an improper setting of the clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does not support changing rates yet. To overcome this issue, a fixed clock can be used for the kernel clock. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 372a99d9cc5c3730e8fbeddeb6134a3b18d938b6..b44ff221e0da968be104ff8195f9bef79c90c57a 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ clk_rcbsec: clk-rcbsec { compatible = "fixed-clock"; clock-frequency = <64000000>; }; + + clk_flexgen_27_fixed: clk-54000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + }; }; firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index f689b47c5010033120146cf1954d6624c0270045..48a95af1741c42300195b753b710e714abc60d96 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,6 +5,12 @@ */ #include "stm32mp253.dtsi" +<dc { + compatible = "st,stm32mp255-ltdc"; + clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; + clock-names = "lcd", "bus", "ref", "lvds"; +}; + &rifsc { vdec: vdec@480d0000 { compatible = "st,stm32mp25-vdec"; -- 2.25.1