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From: kernel test robot <lkp@intel.com>
To: hans.zhang@cixtech.com, bhelgaas@google.com,
	lpieralisi@kernel.org, kw@linux.com, mani@kernel.org,
	robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org
Cc: oe-kbuild-all@lists.linux.dev, mpillai@cadence.com,
	fugang.duan@cixtech.com, guoyin.chen@cixtech.com,
	peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, Hans Zhang <hans.zhang@cixtech.com>
Subject: Re: [PATCH v8 08/15] PCI: cadence: Add support for High Perf Architecture (HPA) controller
Date: Tue, 26 Aug 2025 20:08:30 +0800	[thread overview]
Message-ID: <202508261955.U9IomdXb-lkp@intel.com> (raw)
In-Reply-To: <20250819115239.4170604-9-hans.zhang@cixtech.com>

Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on be48bcf004f9d0c9207ff21d0edb3b42f253829e]

url:    https://github.com/intel-lab-lkp/linux/commits/hans-zhang-cixtech-com/PCI-cadence-Add-module-support-for-platform-controller-driver/20250819-200002
base:   be48bcf004f9d0c9207ff21d0edb3b42f253829e
patch link:    https://lore.kernel.org/r/20250819115239.4170604-9-hans.zhang%40cixtech.com
patch subject: [PATCH v8 08/15] PCI: cadence: Add support for High Perf Architecture (HPA) controller
config: powerpc-randconfig-001-20250826 (https://download.01.org/0day-ci/archive/20250826/202508261955.U9IomdXb-lkp@intel.com/config)
compiler: powerpc-linux-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250826/202508261955.U9IomdXb-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508261955.U9IomdXb-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from <command-line>:
   drivers/pci/controller/cadence/pcie-cadence-hpa.c: In function 'cdns_pcie_hpa_set_outbound_region':
>> include/linux/compiler_types.h:572:38: error: call to '__compiletime_assert_488' declared with attribute error: FIELD_PREP: value too large for the field
     _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
                                         ^
   include/linux/compiler_types.h:553:4: note: in definition of macro '__compiletime_assert'
       prefix ## suffix();    \
       ^~~~~~
   include/linux/compiler_types.h:572:2: note: in expansion of macro '_compiletime_assert'
     _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
     ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
    #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
                                        ^~~~~~~~~~~~~~~~~~
   include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?  \
      ^~~~~~~~~~~~~~~~
   include/linux/bitfield.h:115:3: note: in expansion of macro '__BF_FIELD_CHECK'
      __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
      ^~~~~~~~~~~~~~~~
   drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h:147:2: note: in expansion of macro 'FIELD_PREP'
     FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK, ((nbits) - 1))
     ^~~~~~~~~~
   drivers/pci/controller/cadence/pcie-cadence-hpa.c:129:10: note: in expansion of macro 'CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS'
     addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


vim +/__compiletime_assert_488 +572 include/linux/compiler_types.h

eb5c2d4b45e3d2 Will Deacon 2020-07-21  558  
eb5c2d4b45e3d2 Will Deacon 2020-07-21  559  #define _compiletime_assert(condition, msg, prefix, suffix) \
eb5c2d4b45e3d2 Will Deacon 2020-07-21  560  	__compiletime_assert(condition, msg, prefix, suffix)
eb5c2d4b45e3d2 Will Deacon 2020-07-21  561  
eb5c2d4b45e3d2 Will Deacon 2020-07-21  562  /**
eb5c2d4b45e3d2 Will Deacon 2020-07-21  563   * compiletime_assert - break build and emit msg if condition is false
eb5c2d4b45e3d2 Will Deacon 2020-07-21  564   * @condition: a compile-time constant condition to check
eb5c2d4b45e3d2 Will Deacon 2020-07-21  565   * @msg:       a message to emit if condition is false
eb5c2d4b45e3d2 Will Deacon 2020-07-21  566   *
eb5c2d4b45e3d2 Will Deacon 2020-07-21  567   * In tradition of POSIX assert, this macro will break the build if the
eb5c2d4b45e3d2 Will Deacon 2020-07-21  568   * supplied condition is *false*, emitting the supplied error message if the
eb5c2d4b45e3d2 Will Deacon 2020-07-21  569   * compiler has support to do so.
eb5c2d4b45e3d2 Will Deacon 2020-07-21  570   */
eb5c2d4b45e3d2 Will Deacon 2020-07-21  571  #define compiletime_assert(condition, msg) \
eb5c2d4b45e3d2 Will Deacon 2020-07-21 @572  	_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
eb5c2d4b45e3d2 Will Deacon 2020-07-21  573  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

  reply	other threads:[~2025-08-26 12:08 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-19 11:52 [PATCH v8 00/15] Enhance the PCIe controller driver for next generation controllers hans.zhang
2025-08-19 11:52 ` [PATCH v8 01/15] PCI: cadence: Add module support for platform controller driver hans.zhang
2025-08-19 11:52 ` [PATCH v8 02/15] PCI: cadence: Split PCIe controller header file hans.zhang
2025-08-19 11:52 ` [PATCH v8 03/15] PCI: cadence: Add register definitions for High Perf Architecture (HPA) hans.zhang
2025-08-19 17:36   ` ALOK TIWARI
2025-08-20  8:14     ` Manikandan Karunakaran Pillai
2025-08-19 11:52 ` [PATCH v8 04/15] PCI: cadence: Add helper functions for supporting " hans.zhang
2025-08-19 11:52 ` [PATCH v8 05/15] PCI: cadence: Move PCIe EP common functions to a separate file hans.zhang
2025-08-19 17:46   ` ALOK TIWARI
2025-08-19 11:52 ` [PATCH v8 06/15] PCI: cadence: Move PCIe RP " hans.zhang
2025-08-30 10:36   ` Manivannan Sadhasivam
2025-09-01  4:30     ` Manikandan Karunakaran Pillai
2025-08-19 11:52 ` [PATCH v8 07/15] PCI: cadence: Move PCIe controller common functions as " hans.zhang
2025-08-30 11:21   ` Manivannan Sadhasivam
2025-09-01  4:30     ` Manikandan Karunakaran Pillai
2025-08-19 11:52 ` [PATCH v8 08/15] PCI: cadence: Add support for High Perf Architecture (HPA) controller hans.zhang
2025-08-26 12:08   ` kernel test robot [this message]
2025-08-30 13:18   ` Manivannan Sadhasivam
2025-09-01  4:34     ` Manikandan Karunakaran Pillai
2025-08-19 11:52 ` [PATCH v8 09/15] PCI: cadence: Update PCIe platform to use register offsets passed hans.zhang
2025-08-19 11:52 ` [PATCH v8 10/15] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-08-20  7:23   ` Krzysztof Kozlowski
2025-08-19 11:52 ` [PATCH v8 11/15] PCI: Add Cix Technology Vendor and Device ID hans.zhang
2025-08-30 13:20   ` Manivannan Sadhasivam
2025-08-30 13:21   ` Manivannan Sadhasivam
2025-09-01  3:03     ` Hans Zhang
2025-08-19 11:52 ` [PATCH v8 12/15] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-08-30 13:29   ` Manivannan Sadhasivam
2025-09-01  3:04     ` Hans Zhang
2025-08-19 11:52 ` [PATCH v8 13/15] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-08-19 11:52 ` [PATCH v8 14/15] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-08-30 13:31   ` Manivannan Sadhasivam
2025-09-01  3:09     ` Hans Zhang
2025-08-19 11:52 ` [PATCH v8 15/15] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-08-30 13:33   ` Manivannan Sadhasivam
2025-09-01  3:14     ` Hans Zhang
2025-09-01  3:17       ` Hans Zhang
2025-08-30 13:38 ` [PATCH v8 00/15] Enhance the PCIe controller driver for next generation controllers Manivannan Sadhasivam
2025-09-01  4:28   ` Manikandan Karunakaran Pillai

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