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X-CSE-ConnectionGUID: sjQds6iUQZez82b5lqcrcA== X-CSE-MsgGUID: 6/Pvy7W8SXGbASoDRsF50Q== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="58383031" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="58383031" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Aug 2025 05:08:45 -0700 X-CSE-ConnectionGUID: gkaHm60NTMOz/UaLFOsV6A== X-CSE-MsgGUID: YY4AsznZRwqM3M0+CZ4cpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,214,1751266800"; d="scan'208";a="169736257" Received: from lkp-server02.sh.intel.com (HELO 4ea60e6ab079) ([10.239.97.151]) by orviesa008.jf.intel.com with ESMTP; 26 Aug 2025 05:08:41 -0700 Received: from kbuild by 4ea60e6ab079 with local (Exim 4.96) (envelope-from ) id 1uqsTe-000PIB-0i; Tue, 26 Aug 2025 12:08:38 +0000 Date: Tue, 26 Aug 2025 20:08:30 +0800 From: kernel test robot To: hans.zhang@cixtech.com, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: oe-kbuild-all@lists.linux.dev, mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: Re: [PATCH v8 08/15] PCI: cadence: Add support for High Perf Architecture (HPA) controller Message-ID: <202508261955.U9IomdXb-lkp@intel.com> References: <20250819115239.4170604-9-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250819115239.4170604-9-hans.zhang@cixtech.com> Hi, kernel test robot noticed the following build errors: [auto build test ERROR on be48bcf004f9d0c9207ff21d0edb3b42f253829e] url: https://github.com/intel-lab-lkp/linux/commits/hans-zhang-cixtech-com/PCI-cadence-Add-module-support-for-platform-controller-driver/20250819-200002 base: be48bcf004f9d0c9207ff21d0edb3b42f253829e patch link: https://lore.kernel.org/r/20250819115239.4170604-9-hans.zhang%40cixtech.com patch subject: [PATCH v8 08/15] PCI: cadence: Add support for High Perf Architecture (HPA) controller config: powerpc-randconfig-001-20250826 (https://download.01.org/0day-ci/archive/20250826/202508261955.U9IomdXb-lkp@intel.com/config) compiler: powerpc-linux-gcc (GCC) 8.5.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250826/202508261955.U9IomdXb-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202508261955.U9IomdXb-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from : drivers/pci/controller/cadence/pcie-cadence-hpa.c: In function 'cdns_pcie_hpa_set_outbound_region': >> include/linux/compiler_types.h:572:38: error: call to '__compiletime_assert_488' declared with attribute error: FIELD_PREP: value too large for the field _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^ include/linux/compiler_types.h:553:4: note: in definition of macro '__compiletime_assert' prefix ## suffix(); \ ^~~~~~ include/linux/compiler_types.h:572:2: note: in expansion of macro '_compiletime_assert' _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^~~~~~~~~~~~~~~~~~~ include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert' #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) ^~~~~~~~~~~~~~~~~~ include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG' BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \ ^~~~~~~~~~~~~~~~ include/linux/bitfield.h:115:3: note: in expansion of macro '__BF_FIELD_CHECK' __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ ^~~~~~~~~~~~~~~~ drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h:147:2: note: in expansion of macro 'FIELD_PREP' FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK, ((nbits) - 1)) ^~~~~~~~~~ drivers/pci/controller/cadence/pcie-cadence-hpa.c:129:10: note: in expansion of macro 'CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS' addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ vim +/__compiletime_assert_488 +572 include/linux/compiler_types.h eb5c2d4b45e3d2 Will Deacon 2020-07-21 558 eb5c2d4b45e3d2 Will Deacon 2020-07-21 559 #define _compiletime_assert(condition, msg, prefix, suffix) \ eb5c2d4b45e3d2 Will Deacon 2020-07-21 560 __compiletime_assert(condition, msg, prefix, suffix) eb5c2d4b45e3d2 Will Deacon 2020-07-21 561 eb5c2d4b45e3d2 Will Deacon 2020-07-21 562 /** eb5c2d4b45e3d2 Will Deacon 2020-07-21 563 * compiletime_assert - break build and emit msg if condition is false eb5c2d4b45e3d2 Will Deacon 2020-07-21 564 * @condition: a compile-time constant condition to check eb5c2d4b45e3d2 Will Deacon 2020-07-21 565 * @msg: a message to emit if condition is false eb5c2d4b45e3d2 Will Deacon 2020-07-21 566 * eb5c2d4b45e3d2 Will Deacon 2020-07-21 567 * In tradition of POSIX assert, this macro will break the build if the eb5c2d4b45e3d2 Will Deacon 2020-07-21 568 * supplied condition is *false*, emitting the supplied error message if the eb5c2d4b45e3d2 Will Deacon 2020-07-21 569 * compiler has support to do so. eb5c2d4b45e3d2 Will Deacon 2020-07-21 570 */ eb5c2d4b45e3d2 Will Deacon 2020-07-21 571 #define compiletime_assert(condition, msg) \ eb5c2d4b45e3d2 Will Deacon 2020-07-21 @572 _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) eb5c2d4b45e3d2 Will Deacon 2020-07-21 573 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki