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a=ed25519-sha256; t=1756366503; l=5373; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=nfRxF5NGtqrSzfg0wLCafldDGtD2uBMbtfCRBPzXISs=; b=L7J+dI+faUp/nAQMwdwLGe8DGzvO32BRkKBYbpuJABhKNmoOBQtyPXIpAGx/jAv/4KY4bFMrs ggla+6hpYmtDlXxaK1N7FBpw/daGBl2UGrzwd8D2w7AqXvMBXJVVBI1 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Authority-Analysis: v=2.4 cv=cLDgskeN c=1 sm=1 tr=0 ts=68b006af cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=eK1vwzyvm-k7PeNkGdoA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI2MDE1MyBTYWx0ZWRfX/nODevTbRbEJ ryHB4L2dskBinc+9tdSERn74KUSZFII+I/HBUMDFbLezFAz1W54LRZKybpymCdnxGoFKe0FWFxA 9luXoCPk/4z5q5TQJ4ZCCqwaGLIopxR9g7symaSgqkxVTLI8+frCo3/w4cM4CKtIaktKM++U1fH 4yfOMs8n4hAPYXeMBAAeXmctzQOmBZMEI3qZUb41L10lsilBMZwUhiKjMH7MpWF1xgvc2wtC/bj h6jGB1STA1uR3cYyaFS8xxEUYuTo5SWl26huzBgMYK0l9zAeaiU3J1mVpkbzyLKxbFyCkz0UkAP x61UTVO1s9DKBYJ+AHzzA4AfGcHn0ceUtQXEvhC7wCfJoF/R6fONqUow4MObGUJtFvVub0Cao3t np6lhrYY X-Proofpoint-GUID: 9vH-evrbQPkKasN3A_c75hoto_9aEwQd X-Proofpoint-ORIG-GUID: 9vH-evrbQPkKasN3A_c75hoto_9aEwQd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-28_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508260153 The current implementation requires iATU for every configuration space access which increases latency & cpu utilization. Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature, which shifts/maps the BDF (bits [31:16] of the third header DWORD, which would be matched against the Base and Limit addresses) of the incoming CfgRd0/CfgWr0 down to bits[27:12]of the translated address. Configuring iATU in config shift mode enables ECAM feature to access the config space, which avoids iATU configuration for every config access. Add cfg_shft_mode into struct dw_pcie_ob_atu_cfg to enable config shift mode. As DBI comes under config space, this avoids remapping of DBI space separately. Instead, it uses the mapped config space address returned from ECAM initialization. Change the order of dw_pcie_get_resources() execution to acheive this. Enable the ECAM feature if the config space size is equal to size required to represent number of buses in the bus range property. ELBI registers are optional registers which are part of dwc. So move ELBI resource mapping to dwc. Also change the dtbinding and devicetree to make the elbi registers as optional one. Having ELBI as the required one is making the ecam feature complicated. The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register gives us the offset from which ELBI starts. so use this offset and cfg win to map these regions instead of doing the ioremap again. On root bus, we have only the root port. Any access other than that should not go out of the link and should return all F's. Since the iATU is configured for the buses which starts after root bus, block the transactions starting from function 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb to dbi_base + 1MB) from going outside the link through ECAM blocker through PARF registers. Increase the configuration size to 256MB as required by the ECAM feature and also move config space, DBI, iATU to upper space and use lower space entirely for BAR region. Signed-off-by: Krishna Chaitanya Chundru --- Changes in v8: - Added 256MB alignment check for config space address (Mayank). - Link to v7: https://lore.kernel.org/r/20250822-ecam_v4-v7-0-098fb4ca77c1@oss.qualcomm.com Changes in v7: - Rebased with the latest kernel. - change ecam_mode to ecam_enabled (Konrad) - change dw_pcie_ecam_supported to dw_pcie_ecam_enabled - use FIELD_GET & GENMASK for reading elbi offset (Konrad) - Link to v6: https://lore.kernel.org/r/20250712-ecam_v4-v6-0-d820f912e354@qti.qualcomm.com Changes in v6: - Remove the dtbinding and dt changes which make elbi optional - Use non overlap region in the devicetree and in the driver ELBI registers will be overridden using offset of elbi from dbi start using parf registers (mani). - Link to v5: https://lore.kernel.org/r/20250309-ecam_v4-v5-0-8eff4b59790d@oss.qualcomm.com Changes in v5: - Make elbi as optional and move resource mapping to the dwc (Mani) - Make the changes in the code as we made elbi as optional. - Link to v4: https://lore.kernel.org/r/20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com Changes in v4: - Update the commit messgaes and do minor code changes like adding export for the api, adding error message( mani) - Link to v3: https://lore.kernel.org/all/20250121-enable_ecam-v3-0-cd84d3b2a7ba@oss.qualcomm.com/ Changes in v3: - if bus range is less than 2 return with out configuring iATU for next bus & update the logic of ecam_supported() as suggested ( Konrad) - updated commit text and update S-o-b (Bjorn Andresson) - Link to v2: https://lore.kernel.org/r/20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com changes in v2: - rename enable_ecam to ecam_mode as suggested by mani. - refactor changes as suggested by bjorn - remove ecam_init() function op as we have removed ELBI virtual address update from the ecam_init and moved to host init as we need the clocks to be enabled to read the ELBI offset from the PARF registers. - Update comments and commit message as suggested by bjorn. - Allocate host bridge in the DWC glue drivers as suggested by bjorn - move qcom_pcie_ecam_supported to dwc as suggested by mani. Link to v1: https://lore.kernel.org/r/linux-devicetree/20241117-ecam-v1-1-6059faf38d07@quicinc.com/T/ --- Krishna Chaitanya Chundru (5): arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature PCI: dwc: Add support for ELBI resource mapping PCI: dwc: qcom: Switch to dwc ELBI resource mapping PCI: dwc: Add ECAM support with iATU configuration PCI: qcom: Add support for ECAM feature arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 +-- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-designware-host.c | 145 +++++++++++++++++++--- drivers/pci/controller/dwc/pcie-designware.c | 11 +- drivers/pci/controller/dwc/pcie-designware.h | 6 + drivers/pci/controller/dwc/pcie-qcom.c | 86 +++++++++++-- 6 files changed, 232 insertions(+), 31 deletions(-) --- base-commit: 07d9df80082b8d1f37e05658371b087cb6738770 change-id: 20250207-ecam_v4-f4eb9b893eeb Best regards, -- Krishna Chaitanya Chundru