[PATCH v5 0/5] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors)

[Denzeel Oliva <wachiturroxd150@gmail.com>]

Hi,

Two small fixes for Exynos990 CMU_TOP:

Correct PLL mux register selection (use PLL_CON0), add DPU_BUS and
CMUREF mux/div, and update clock IDs.
Fix mux/div bit widths and replace a few bogus divs with fixed-factor
clocks (HSI1/2 PCIe, USBDP debug); also fix OTP rate.

Changes in v2:

- In the first commit the divratio of
  PLL_SHARED0_DIV3 should not be changed.

Changes in v3:

- There is no ABI massive break, the new ID clocks are
  in the last define CMU_TOP block.

Changes in v4:

- Fix compilation for define CLK_DOUT_CMU_CMUREF to
  CLK_DOUT_CMU_CLK_CMUREF

Changes in v5:

-  Rewrite commits and remove cosmetic/non-operational changes
   and unrelated rebases.
   CLKS_NR_TOP will be moved to the patch that adds the new clocks.

Please review.

Denzeel Oliva

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
---
Denzeel Oliva (5):
      clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
      clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
      clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
      dt-bindings: clock: exynos990: Extend clocks IDs
      clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP

 drivers/clk/samsung/clk-exynos990.c           | 80 ++++++++++++++++++++-------
 include/dt-bindings/clock/samsung,exynos990.h |  4 ++
 2 files changed, 63 insertions(+), 21 deletions(-)
---
base-commit: 39f90c1967215375f7d87b81d14b0f3ed6b40c29
change-id: 20250830-fix-cmu-top-0917aa84871b

Best regards,
-- 
Denzeel Oliva <wachiturroxd150@gmail.com>