* [PATCH 0/4] riscv: Add Zalasr ISA exntesion support
@ 2025-09-01 11:30 Xu Lu
2025-09-01 11:30 ` [PATCH 1/4] riscv: add ISA extension parsing for Zalasr Xu Lu
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Xu Lu @ 2025-09-01 11:30 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, paul.walmsley, palmer, aou, alex, ajones,
brs
Cc: devicetree, linux-riscv, linux-kernel, apw, joe, Xu Lu
This patch adds support for the Zalasr ISA extension, which supplies the
real load acquire/store release instructions.
The specification can be found here:
https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
This patch seires has been tested with ltp on Qemu with Brensan's zalasr
support patch[1].
Some false positive spacing error happens during patch checking. Thus I
CCed maintainers of checkpatch.pl as well.
[1] https://lore.kernel.org/all/CAGPSXwJEdtqW=nx71oufZp64nK6tK=0rytVEcz4F-gfvCOXk2w@mail.gmail.com/
Xu Lu (4):
riscv: add ISA extension parsing for Zalasr
dt-bindings: riscv: Add Zalasr ISA extension description
riscv: Instroduce Zalasr instructions
riscv: Use Zalasr for smp_load_acquire/smp_store_release
.../devicetree/bindings/riscv/extensions.yaml | 5 ++
arch/riscv/include/asm/barrier.h | 79 ++++++++++++++++---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++
arch/riscv/kernel/cpufeature.c | 1 +
5 files changed, 154 insertions(+), 11 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] riscv: add ISA extension parsing for Zalasr
2025-09-01 11:30 [PATCH 0/4] riscv: Add Zalasr ISA exntesion support Xu Lu
@ 2025-09-01 11:30 ` Xu Lu
2025-09-01 11:30 ` [PATCH 2/4] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Xu Lu @ 2025-09-01 11:30 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, paul.walmsley, palmer, aou, alex, ajones,
brs
Cc: devicetree, linux-riscv, linux-kernel, apw, joe, Xu Lu
Add parsing for Zalasr ISA extension.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index affd63e11b0a3..ae3852c4f2ca2 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -106,6 +106,7 @@
#define RISCV_ISA_EXT_ZAAMO 97
#define RISCV_ISA_EXT_ZALRSC 98
#define RISCV_ISA_EXT_ZICBOP 99
+#define RISCV_ISA_EXT_ZALASR 100
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 743d53415572e..bf9d3d92bf372 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -472,6 +472,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
+ __RISCV_ISA_EXT_DATA(zalasr, RISCV_ISA_EXT_ZALASR),
__RISCV_ISA_EXT_DATA(zalrsc, RISCV_ISA_EXT_ZALRSC),
__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] dt-bindings: riscv: Add Zalasr ISA extension description
2025-09-01 11:30 [PATCH 0/4] riscv: Add Zalasr ISA exntesion support Xu Lu
2025-09-01 11:30 ` [PATCH 1/4] riscv: add ISA extension parsing for Zalasr Xu Lu
@ 2025-09-01 11:30 ` Xu Lu
2025-09-01 18:44 ` Conor Dooley
2025-09-01 11:30 ` [PATCH 3/4] riscv: Instroduce Zalasr instructions Xu Lu
2025-09-01 11:30 ` [PATCH 4/4] riscv: Use Zalasr for smp_load_acquire/smp_store_release Xu Lu
3 siblings, 1 reply; 6+ messages in thread
From: Xu Lu @ 2025-09-01 11:30 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, paul.walmsley, palmer, aou, alex, ajones,
brs
Cc: devicetree, linux-riscv, linux-kernel, apw, joe, Xu Lu
Add description for the Zalasr ISA extension
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ede6a58ccf534..6b8c21807a2da 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -248,6 +248,11 @@ properties:
ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text
(#1304)") of the unprivileged ISA specification.
+ - const: zalasr
+ description: |
+ The standard Zalasr extension for load-acquire/store-release as frozen
+ at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
+
- const: zawrs
description: |
The Zawrs extension for entering a low-power state or for trapping
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] riscv: Instroduce Zalasr instructions
2025-09-01 11:30 [PATCH 0/4] riscv: Add Zalasr ISA exntesion support Xu Lu
2025-09-01 11:30 ` [PATCH 1/4] riscv: add ISA extension parsing for Zalasr Xu Lu
2025-09-01 11:30 ` [PATCH 2/4] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
@ 2025-09-01 11:30 ` Xu Lu
2025-09-01 11:30 ` [PATCH 4/4] riscv: Use Zalasr for smp_load_acquire/smp_store_release Xu Lu
3 siblings, 0 replies; 6+ messages in thread
From: Xu Lu @ 2025-09-01 11:30 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, paul.walmsley, palmer, aou, alex, ajones,
brs
Cc: devicetree, linux-riscv, linux-kernel, apw, joe, Xu Lu
Introduce l{b|h|w|d}.{aq|aqrl} and s{b|h|w|d}.{rl|aqrl} instruction
encodings.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
index d5adbaec1d010..3fec7e66ce50f 100644
--- a/arch/riscv/include/asm/insn-def.h
+++ b/arch/riscv/include/asm/insn-def.h
@@ -179,6 +179,7 @@
#define RV___RS1(v) __RV_REG(v)
#define RV___RS2(v) __RV_REG(v)
+#define RV_OPCODE_AMO RV_OPCODE(47)
#define RV_OPCODE_MISC_MEM RV_OPCODE(15)
#define RV_OPCODE_OP_IMM RV_OPCODE(19)
#define RV_OPCODE_SYSTEM RV_OPCODE(115)
@@ -208,6 +209,84 @@
__ASM_STR(.error "hlv.d requires 64-bit support")
#endif
+#define LB_AQ(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LB_AQRL(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LH_AQ(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LH_AQRL(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LW_AQ(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LW_AQRL(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define SB_RL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SB_AQRL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SH_RL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SH_AQRL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SW_RL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SW_AQRL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31), \
+ __RD(0), RS1(addr), RS2(src))
+
+#ifdef CONFIG_64BIT
+#define LD_AQ(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define LD_AQRL(dest, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27), \
+ RD(dest), RS1(addr), __RS2(0))
+
+#define SD_RL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29), \
+ __RD(0), RS1(addr), RS2(src))
+
+#define SD_AQRL(src, addr) \
+ INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31), \
+ __RD(0), RS1(addr), RS2(src))
+#else
+#define LD_AQ(dest, addr) \
+ __ASM_STR(.error "ld.aq requires 64-bit support")
+
+#define LD_AQRL(dest, addr) \
+ __ASM_STR(.error "ld.aqrl requires 64-bit support")
+
+#define SD_RL(dest, addr) \
+ __ASM_STR(.error "sd.rl requires 64-bit support")
+
+#define SD_AQRL(dest, addr) \
+ __ASM_STR(.error "sd.aqrl requires 64-bit support")
+#endif
+
#define SINVAL_VMA(vaddr, asid) \
INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \
__RD(0), RS1(vaddr), RS2(asid))
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] riscv: Use Zalasr for smp_load_acquire/smp_store_release
2025-09-01 11:30 [PATCH 0/4] riscv: Add Zalasr ISA exntesion support Xu Lu
` (2 preceding siblings ...)
2025-09-01 11:30 ` [PATCH 3/4] riscv: Instroduce Zalasr instructions Xu Lu
@ 2025-09-01 11:30 ` Xu Lu
3 siblings, 0 replies; 6+ messages in thread
From: Xu Lu @ 2025-09-01 11:30 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, paul.walmsley, palmer, aou, alex, ajones,
brs
Cc: devicetree, linux-riscv, linux-kernel, apw, joe, Xu Lu
Replace fence instructions with Zalasr instructions during acquire or
release operations.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/include/asm/barrier.h | 79 +++++++++++++++++++++++++++-----
1 file changed, 68 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
index b8c5726d86acb..b1d2a9a85256d 100644
--- a/arch/riscv/include/asm/barrier.h
+++ b/arch/riscv/include/asm/barrier.h
@@ -51,19 +51,76 @@
*/
#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw)
-#define __smp_store_release(p, v) \
-do { \
- compiletime_assert_atomic_type(*p); \
- RISCV_FENCE(rw, w); \
- WRITE_ONCE(*p, v); \
+extern void __bad_size_call_parameter(void);
+
+#define __smp_store_release(p, v) \
+do { \
+ compiletime_assert_atomic_type(*p); \
+ switch (sizeof(*p)) { \
+ case 1: \
+ asm volatile(ALTERNATIVE("fence rw, w;\t\nsb %0, 0(%1)\t\n", \
+ SB_RL(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : : "r" (v), "r" (p) : "memory"); \
+ break; \
+ case 2: \
+ asm volatile(ALTERNATIVE("fence rw, w;\t\nsh %0, 0(%1)\t\n", \
+ SH_RL(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : : "r" (v), "r" (p) : "memory"); \
+ break; \
+ case 4: \
+ asm volatile(ALTERNATIVE("fence rw, w;\t\nsw %0, 0(%1)\t\n", \
+ SW_RL(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : : "r" (v), "r" (p) : "memory"); \
+ break; \
+ case 8: \
+ asm volatile(ALTERNATIVE("fence rw, w;\t\nsd %0, 0(%1)\t\n", \
+ SD_RL(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : : "r" (v), "r" (p) : "memory"); \
+ break; \
+ default: \
+ __bad_size_call_parameter(); \
+ break; \
+ } \
} while (0)
-#define __smp_load_acquire(p) \
-({ \
- typeof(*p) ___p1 = READ_ONCE(*p); \
- compiletime_assert_atomic_type(*p); \
- RISCV_FENCE(r, rw); \
- ___p1; \
+#define __smp_load_acquire(p) \
+({ \
+ TYPEOF_UNQUAL(*p) val; \
+ compiletime_assert_atomic_type(*p); \
+ switch (sizeof(*p)) { \
+ case 1: \
+ asm volatile(ALTERNATIVE("lb %0, 0(%1)\t\nfence r, rw\t\n", \
+ LB_AQ(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : "=r" (val) : "r" (p) : "memory"); \
+ break; \
+ case 2: \
+ asm volatile(ALTERNATIVE("lh %0, 0(%1)\t\nfence r, rw\t\n", \
+ LH_AQ(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : "=r" (val) : "r" (p) : "memory"); \
+ break; \
+ case 4: \
+ asm volatile(ALTERNATIVE("lw %0, 0(%1)\t\nfence r, rw\t\n", \
+ LW_AQ(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : "=r" (val) : "r" (p) : "memory"); \
+ break; \
+ case 8: \
+ asm volatile(ALTERNATIVE("ld %0, 0(%1)\t\nfence r, rw\t\n", \
+ LD_AQ(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : "=r" (val) : "r" (p) : "memory"); \
+ break; \
+ default: \
+ __bad_size_call_parameter(); \
+ break; \
+ } \
+ val; \
})
#ifdef CONFIG_RISCV_ISA_ZAWRS
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/4] dt-bindings: riscv: Add Zalasr ISA extension description
2025-09-01 11:30 ` [PATCH 2/4] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
@ 2025-09-01 18:44 ` Conor Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2025-09-01 18:44 UTC (permalink / raw)
To: Xu Lu
Cc: robh, krzk+dt, conor+dt, paul.walmsley, palmer, aou, alex, ajones,
brs, devicetree, linux-riscv, linux-kernel, apw, joe
[-- Attachment #1: Type: text/plain, Size: 1221 bytes --]
On Mon, Sep 01, 2025 at 07:30:20PM +0800, Xu Lu wrote:
> Add description for the Zalasr ISA extension
>
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index ede6a58ccf534..6b8c21807a2da 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -248,6 +248,11 @@ properties:
> ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text
> (#1304)") of the unprivileged ISA specification.
>
> + - const: zalasr
This is out of order, no? zalrsc would come after zalasr.
> + description: |
> + The standard Zalasr extension for load-acquire/store-release as frozen
> + at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
> +
> - const: zawrs
> description: |
> The Zawrs extension for entering a low-power state or for trapping
> --
> 2.20.1
>
[-- Attachment #2: signature.asc --]
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2025-09-01 18:44 ` Conor Dooley
2025-09-01 11:30 ` [PATCH 3/4] riscv: Instroduce Zalasr instructions Xu Lu
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