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Mon, 01 Sep 2025 04:30:45 -0700 (PDT) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.55]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7725ad1e9afsm2911441b3a.11.2025.09.01.04.30.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 01 Sep 2025 04:30:45 -0700 (PDT) From: Xu Lu To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, ajones@ventanamicro.com, brs@rivosinc.com Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com, Xu Lu Subject: [PATCH 2/4] dt-bindings: riscv: Add Zalasr ISA extension description Date: Mon, 1 Sep 2025 19:30:20 +0800 Message-Id: <20250901113022.3812-3-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250901113022.3812-1-luxu.kernel@bytedance.com> References: <20250901113022.3812-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add description for the Zalasr ISA extension Signed-off-by: Xu Lu --- Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index ede6a58ccf534..6b8c21807a2da 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -248,6 +248,11 @@ properties: ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)") of the unprivileged ISA specification. + - const: zalasr + description: | + The standard Zalasr extension for load-acquire/store-release as frozen + at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. + - const: zawrs description: | The Zawrs extension for entering a low-power state or for trapping -- 2.20.1