[PATCH 00/19] Add clock and reset support for Mobileye eyeQ7H

["Benoît Monin" <benoit.monin@bootlin.com>]

This patchset brings the support of the OLB found in the new Mobileye SoC,
the eyeQ7H. Those Other Logic Blocks provide clock and reset functions
to the controllers of the chip. This series also contains changes to the
clock driver and its device tree binding to better match the hardware
found in the eyeQ chips.

In details, patches 1 and 2 rename the dt-binding yaml and header to
eyeq-olb.yaml and eyeq-clk.h. We drop the "5" from the filename since
the binding also applies to other eyeQ SoC (eyeQ6L, eyeQ6H and eyeQ7H).

Patches 3 and 4 add the compatibles entries and the clock indexes to
the dt-binding for the eyeQ7H.

Patch 5 introduces a dt-binding header for the reset indexes of the
eyeQ7H, similar to the header of the clock indexes.

Patch 6 adds the compatible entries to the reset-eyeq driver, and the
needed changes for the reset domain found in the eyeQ7H.

Patch 7 adds clk_hw_register_fixed_factor_with_accuracy to
clk-fixed-factor.c. This function allows registering a fixed factor with
both a parent clock and a known accuracy. This will be used to register
clocks referring to a parent clock registered in early init.

Patch 8 and 9 add validity checks to clk-divider.c. The first ensure that
the divider is even if the flag CLK_DIVIDER_EVEN_INTEGERS is set. The
second rejects the registration of clock with both a table and a flag set
if the flag leads to the table being ignored when computing the divider.

Patch 10 removes the post-divisor in the computation of the PLL frequency
in clk-eyeq.c. This change reflects how the clock signal is routed in
the OLB of all eyeQ SoC.

Patch 11 and 12 allow referencing to a parent clock by name for divider
and fixed fixed factor in clk-eyeq.c. This is needed by the eyeQ5 to
refer to clock registered in early init during probe.

Patch 13 to 15 prepare the introduction of new PLL types present in
the eyeQ7H OLB, by prefixing the PLL defines with the PLL type found in
eyeQ5 and eyeQ6 OLB, renaming the reg64 field and adding a type field
in eqc_pll.

Patch 16 adds the two PLL types found in the eyeQ7H to the clk-eyeq
driver.

Patch 17 adds a parent_name field to the eqc_pll structure. This will
be used to refer to other parent clock for the PLL found in the OLB of
the eyeQ7H.

Patch 18 adds an optional clk_div_table to divider in the clk-eyeq driver.

Finally, patch 19 declares all the compatible entries for the OLB of the
eyeQ7H in the clk-eyeq driver, making use of the changes introduced in
the previous patches.

To: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
To: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Théo Lebrun <theo.lebrun@bootlin.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Tawfik Bayouk <tawfik.bayouk@mobileye.com>
Cc: Sari Khoury <sari.khoury@mobileye.com>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-clk@vger.kernel.org

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
Benoît Monin (19):
      dt-bindings: soc: mobileye: rename to eyeq-olb.yaml
      dt-bindings: clock: mobileye: rename to eyeq-clk.h
      dt-bindings: soc: mobileye: add eyeQ7H compatibles
      dt-bindings: clock: mobileye: add eyeQ7H clock indexes
      dt-bindings: reset: add Mobileye eyeQ
      reset: eyeq: add eyeQ7H compatibles
      clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy
      clk: divider: check divider validity for CLK_DIVIDER_EVEN_INTEGERS
      clk: divider: check validity of flags when a table is provided
      clk: eyeq: skip post-divisor when computing pll divisor
      clk: eyeq: rename the parent field to parent_idx
      clk: eyeq: lookup parent clock by name
      clk: eyeq: prefix the PLL registers with the PLL type
      clk: eyeq: rename the reg64 field of eqc_pll
      clk: eyeq: add a type for the PLL
      clk: eyeq: add two PLL types
      clk: eyeq: add a parent field to the pll
      clk: eyeq: add an optional clk_div_table to divider
      clk: eyeq: add eyeQ7H compatibles

 ...ileye,eyeq5-olb.yaml => mobileye,eyeq-olb.yaml} | 137 +++-
 MAINTAINERS                                        |   3 +-
 arch/mips/boot/dts/mobileye/eyeq5.dtsi             |   2 +-
 arch/mips/boot/dts/mobileye/eyeq6h.dtsi            |   2 +-
 drivers/clk/clk-divider.c                          |   9 +
 drivers/clk/clk-eyeq.c                             | 876 ++++++++++++++++++---
 drivers/clk/clk-fixed-factor.c                     |  12 +
 drivers/reset/reset-eyeq.c                         | 248 +++++-
 include/dt-bindings/clock/mobileye,eyeq-clk.h      | 175 ++++
 include/dt-bindings/clock/mobileye,eyeq5-clk.h     |  65 --
 include/dt-bindings/reset/mobileye,eyeq-reset.h    |  75 ++
 include/linux/clk-provider.h                       |   3 +
 12 files changed, 1414 insertions(+), 193 deletions(-)
---
base-commit: b320789d6883cc00ac78ce83bccbfe7ed58afcf0
change-id: 20250807-clk-eyeq7-f9c6ea43d138

Best regards,
-- 
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com