From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC76A3002C6; Wed, 3 Sep 2025 12:47:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903659; cv=none; b=jgzKDoH4/EJDTLtxBTwMh2DosGHIam9mcUofxoCVBNq0j9y93P6oeneHUq/IvnGeA1hnM7dCc6LwArUDOtnc3C+mIDhfzafQSorxC4ETiU5pREQ1Au8owE4/nMKb7u/jmbcviDV+PueahZhyOFCa9JbjTlFTS/OF9SeibhgEptg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903659; c=relaxed/simple; bh=cNRFisRXLFpNEwr6KqKWti7XX70NsMlUMR05LP253yI=; h=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc; b=BObf9FvoqigJYKcAKdPqFwzOhFHx1dey4LW3pEBiwSvi5yTlUFkM75R+m6KTGWPx6B7/F2xTy8iQjucinqh7WK5NAZqBqo41pWQet1k/03LhJNW2HF70fv1i50cG4xMWlzmkoYyuWUwBzVA5TXYDuL37MNa49Vjocnpdss1ehGs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Fo/8eOf/; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Fo/8eOf/" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 3274E1A08CE; Wed, 3 Sep 2025 12:47:35 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id EBF2C606C3; Wed, 3 Sep 2025 12:47:34 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 103D41C22A4EA; Wed, 3 Sep 2025 14:47:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903653; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding; bh=rHZeM7R9CCkA2R4gaMHWa0k676D0il171o0vPPyB7Z8=; b=Fo/8eOf/0cWEkBjA0qSUbhVxlg7jVKPlRWcVOQSlsQb+MmCRXTTdHD2KKJu8Yb31livi6Y Hy+1o13RKmNpQjcf1rMl3WLIwr0a4kBMemtJPwEMCrG251zFZxb/+93pUjZlje3Q6blzNU eTbAqc014QkBS51t75bA04KTRBFV7lT1vqkt1MWY/9pAvLXSBp4KxrQNk/6wA1JkZ6ZTIv nBbYI0Pg2yqtXL7d0oz99EzzAchIGyvl4duifTkgY1azpGLY4uWyrNWyjBXRFev/BfVICO hIaY8Mlh9Ns/Xqn+9F8OQ2eLkxYM9JpV96v+dVUeW1hgrdGFnkd/VwDwXT+tEQ== From: =?utf-8?q?Beno=C3=AEt_Monin?= Subject: [PATCH 00/19] Add clock and reset support for Mobileye eyeQ7H Date: Wed, 03 Sep 2025 14:47:07 +0200 Message-Id: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAMs4uGgC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDCwNz3eScbN3UytRCc900y2Sz1EQT4xRDYwsloPqCotS0zAqwWdGxtbU A62g8/VsAAAA= X-Change-ID: 20250807-clk-eyeq7-f9c6ea43d138 To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 This patchset brings the support of the OLB found in the new Mobileye SoC, the eyeQ7H. Those Other Logic Blocks provide clock and reset functions to the controllers of the chip. This series also contains changes to the clock driver and its device tree binding to better match the hardware found in the eyeQ chips. In details, patches 1 and 2 rename the dt-binding yaml and header to eyeq-olb.yaml and eyeq-clk.h. We drop the "5" from the filename since the binding also applies to other eyeQ SoC (eyeQ6L, eyeQ6H and eyeQ7H). Patches 3 and 4 add the compatibles entries and the clock indexes to the dt-binding for the eyeQ7H. Patch 5 introduces a dt-binding header for the reset indexes of the eyeQ7H, similar to the header of the clock indexes. Patch 6 adds the compatible entries to the reset-eyeq driver, and the needed changes for the reset domain found in the eyeQ7H. Patch 7 adds clk_hw_register_fixed_factor_with_accuracy to clk-fixed-factor.c. This function allows registering a fixed factor with both a parent clock and a known accuracy. This will be used to register clocks referring to a parent clock registered in early init. Patch 8 and 9 add validity checks to clk-divider.c. The first ensure that the divider is even if the flag CLK_DIVIDER_EVEN_INTEGERS is set. The second rejects the registration of clock with both a table and a flag set if the flag leads to the table being ignored when computing the divider. Patch 10 removes the post-divisor in the computation of the PLL frequency in clk-eyeq.c. This change reflects how the clock signal is routed in the OLB of all eyeQ SoC. Patch 11 and 12 allow referencing to a parent clock by name for divider and fixed fixed factor in clk-eyeq.c. This is needed by the eyeQ5 to refer to clock registered in early init during probe. Patch 13 to 15 prepare the introduction of new PLL types present in the eyeQ7H OLB, by prefixing the PLL defines with the PLL type found in eyeQ5 and eyeQ6 OLB, renaming the reg64 field and adding a type field in eqc_pll. Patch 16 adds the two PLL types found in the eyeQ7H to the clk-eyeq driver. Patch 17 adds a parent_name field to the eqc_pll structure. This will be used to refer to other parent clock for the PLL found in the OLB of the eyeQ7H. Patch 18 adds an optional clk_div_table to divider in the clk-eyeq driver. Finally, patch 19 declares all the compatible entries for the OLB of the eyeQ7H in the clk-eyeq driver, making use of the changes introduced in the previous patches. To: Vladimir Kondratiev To: Gregory CLEMENT To: Théo Lebrun To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Thomas Bogendoerfer To: Michael Turquette To: Stephen Boyd To: Philipp Zabel Cc: Thomas Petazzoni Cc: Tawfik Bayouk Cc: Sari Khoury Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Benoît Monin --- Benoît Monin (19): dt-bindings: soc: mobileye: rename to eyeq-olb.yaml dt-bindings: clock: mobileye: rename to eyeq-clk.h dt-bindings: soc: mobileye: add eyeQ7H compatibles dt-bindings: clock: mobileye: add eyeQ7H clock indexes dt-bindings: reset: add Mobileye eyeQ reset: eyeq: add eyeQ7H compatibles clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy clk: divider: check divider validity for CLK_DIVIDER_EVEN_INTEGERS clk: divider: check validity of flags when a table is provided clk: eyeq: skip post-divisor when computing pll divisor clk: eyeq: rename the parent field to parent_idx clk: eyeq: lookup parent clock by name clk: eyeq: prefix the PLL registers with the PLL type clk: eyeq: rename the reg64 field of eqc_pll clk: eyeq: add a type for the PLL clk: eyeq: add two PLL types clk: eyeq: add a parent field to the pll clk: eyeq: add an optional clk_div_table to divider clk: eyeq: add eyeQ7H compatibles ...ileye,eyeq5-olb.yaml => mobileye,eyeq-olb.yaml} | 137 +++- MAINTAINERS | 3 +- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 2 +- arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 2 +- drivers/clk/clk-divider.c | 9 + drivers/clk/clk-eyeq.c | 876 ++++++++++++++++++--- drivers/clk/clk-fixed-factor.c | 12 + drivers/reset/reset-eyeq.c | 248 +++++- include/dt-bindings/clock/mobileye,eyeq-clk.h | 175 ++++ include/dt-bindings/clock/mobileye,eyeq5-clk.h | 65 -- include/dt-bindings/reset/mobileye,eyeq-reset.h | 75 ++ include/linux/clk-provider.h | 3 + 12 files changed, 1414 insertions(+), 193 deletions(-) --- base-commit: b320789d6883cc00ac78ce83bccbfe7ed58afcf0 change-id: 20250807-clk-eyeq7-f9c6ea43d138 Best regards, -- Benoît Monin, Bootlin Embedded Linux and Kernel engineering https://bootlin.com