From: Aaron Kling via B4 Relay <devnull+webgeek1234.gmail.com@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Joseph Lo <josephl@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
Thierry Reding <treding@nvidia.com>,
Aaron Kling <webgeek1234@gmail.com>
Subject: [PATCH v2 4/4] arm64: tegra: Limit max cpu frequency on P3450
Date: Wed, 03 Sep 2025 14:30:19 -0500 [thread overview]
Message-ID: <20250903-tegra210-speedo-v2-4-89e6f86b8942@gmail.com> (raw)
In-Reply-To: <20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com>
From: Aaron Kling <webgeek1234@gmail.com>
P3450's cpu is rated for 1.5 GHz, but due to the passive cooling on the
devkit, the maximum frequency needs limited to 1.4 GHz to maintain
reasonable thermals. Ideally, the dfll driver would adjust based on
temperature reporting, but in the absence of that, this will have to do.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
index ec0e84cb83ef9bf8f0e52e2958db33666813917c..10f878d3f50815d1f0297d15669048ab9cad73ee 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -594,6 +594,7 @@ clock@70110000 {
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,sample-rate = <25000>;
+ nvidia,dfll-max-freq = <1479000000>;
nvidia,pwm-min-microvolts = <708000>;
nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
--
2.50.1
prev parent reply other threads:[~2025-09-03 19:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-03 19:30 [PATCH v2 0/4] Properly Limit Tegra210 Clock Rates Aaron Kling via B4 Relay
2025-09-03 19:30 ` [PATCH v2 1/4] dt-bindings: clock: tegra124-dfll: Add property to limit frequency Aaron Kling via B4 Relay
2025-09-03 20:03 ` Aaron Kling
2025-09-04 19:34 ` Rob Herring
2025-09-04 21:49 ` Rob Herring
2025-09-03 19:30 ` [PATCH v2 2/4] soc: tegra: fuse: speedo-tegra210: Update speedo ids Aaron Kling via B4 Relay
2025-09-03 19:30 ` [PATCH v2 3/4] clk: tegra: dfll: Support limiting max clock per device Aaron Kling via B4 Relay
2025-09-03 19:30 ` Aaron Kling via B4 Relay [this message]
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