From: Conor Dooley <conor@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, E Shattow <e@freeshell.de>
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Hal Feng <hal.feng@starfivetech.com>,
Minda Chen <minda.chen@starfivetech.com>
Subject: Re: [PATCH v3 RESEND 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110
Date: Thu, 4 Sep 2025 18:58:08 +0100 [thread overview]
Message-ID: <20250904-grape-convent-8c36463138e2@spud> (raw)
In-Reply-To: <20250823100159.203925-1-e@freeshell.de>
From: Conor Dooley <conor.dooley@microchip.com>
On Sat, 23 Aug 2025 03:01:40 -0700, E Shattow wrote:
> Bring in additional downstream U-Boot boot loader changes for StarFive
> VisionFive2 board target (and related JH7110 common boards). Create a
> basic dt-binding (and not any Linux driver) in support of the
> memory-controller dts node used in mainline U-Boot. Also add
> bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.
>
> Changes since v2:
>
> [...]
Applied to riscv-dt-for-next, thanks!
[1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
https://git.kernel.org/conor/c/f5e36ecc9e4a
[2/3] riscv: dts: starfive: jh7110: add DMC memory controller
https://git.kernel.org/conor/c/7114969021ec
[3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader
https://git.kernel.org/conor/c/8181cc2f3f21
Thanks,
Conor.
prev parent reply other threads:[~2025-09-04 17:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-23 10:01 [PATCH v3 RESEND 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow
2025-08-23 10:01 ` [PATCH v3 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC E Shattow
2025-08-23 20:41 ` E Shattow
2025-08-24 9:25 ` Krzysztof Kozlowski
2025-08-25 16:25 ` Conor Dooley
2025-08-23 10:01 ` [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow
2025-08-23 17:34 ` Hal Feng
2025-08-23 10:01 ` [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow
2025-08-23 17:36 ` Hal Feng
2025-08-27 17:28 ` [PATCH v3 RESEND 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 Conor Dooley
2025-09-04 9:02 ` Emil Renner Berthing
2025-09-04 17:58 ` Conor Dooley [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250904-grape-convent-8c36463138e2@spud \
--to=conor@kernel.org \
--cc=alex@ghiti.fr \
--cc=aou@eecs.berkeley.edu \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=e@freeshell.de \
--cc=hal.feng@starfivetech.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=minda.chen@starfivetech.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).