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From: Conor Dooley <conor@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	E Shattow <e@freeshell.de>
Cc: conor@kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Hal Feng <hal.feng@starfivetech.com>,
	Minda Chen <minda.chen@starfivetech.com>
Subject: Re: [PATCH v3 RESEND 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110
Date: Thu,  4 Sep 2025 18:58:08 +0100
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From: Conor Dooley <conor.dooley@microchip.com>

On Sat, 23 Aug 2025 03:01:40 -0700, E Shattow wrote:
> Bring in additional downstream U-Boot boot loader changes for StarFive
> VisionFive2 board target (and related JH7110 common boards). Create a
> basic dt-binding (and not any Linux driver) in support of the
> memory-controller dts node used in mainline U-Boot. Also add
> bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.
> 
> Changes since v2:
> 
> [...]

Applied to riscv-dt-for-next, thanks!

[1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
      https://git.kernel.org/conor/c/f5e36ecc9e4a
[2/3] riscv: dts: starfive: jh7110: add DMC memory controller
      https://git.kernel.org/conor/c/7114969021ec
[3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader
      https://git.kernel.org/conor/c/8181cc2f3f21

Thanks,
Conor.