From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 773A11EE019; Fri, 5 Sep 2025 05:15:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757049320; cv=none; b=fTqrA5QVhBcDVrU5VSe+94cViW6hscsN91fPX1dnL11PJOHOC0ejH6e2ng3LnB2gE1zqbwTuQwQwS1REhzYQbd0mRwigvQ4+lMe3c3AKh/OLMI7bUUML2eaZUG3PKXgZgJnx4o83VgyTXawWojXOBR1jKaUsDYzggGvPbvYDZhI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757049320; c=relaxed/simple; bh=VWu4d7GqSUwIeDFUNxrTde8n+HgE4QYouRpf9d/Un3U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HSuCak18SHd7uhGvLDCxkLYNHaJMaLl01Vtde3W6lGhPV4jHi1Il4tF1w1disRG60f/Tvaqc4VO7h1iN1T57c1BfETCKAyT1rdX6y/vGaZe82abdUJRT8T1iflGUYmDo9XWMvYNzFsH0HVO0vkI00BMgdXLpdWKKN4IPWL6NZ4Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=E5jvFdR2; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="E5jvFdR2" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5855FERu3245543; Fri, 5 Sep 2025 00:15:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757049314; bh=cK4uQLEtwZy/fYoLqypop64Y9ZdcTJG2slYJFSfO8Zo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=E5jvFdR2g+4TOLrT7SPflaIigeZMczFg9owmZYRd/8Rn8lY3nOmo83ZlMcBm5l/Xa GckiDnHFuzkVcszUcj3YCaezwmCYUpL6dZvWQgark8igY60EwAyLUBVTjfD+3sW8kV YcE3iQDlORflokDGvNimu8GX/I0XQ+v9xbRlCq60= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5855FEcG134391 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 5 Sep 2025 00:15:14 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 00:15:13 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 00:15:13 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5855Ep0g4118818; Fri, 5 Sep 2025 00:15:09 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , , , CC: Subject: [PATCH v5 2/4] arm64: dts: ti: k3-am62x-sk-common: Remove the unused cfg in USB1_DRVVBUS Date: Fri, 5 Sep 2025 10:44:46 +0530 Message-ID: <20250905051448.2836237-3-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905051448.2836237-1-a-kaur@ti.com> References: <20250905051448.2836237-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. But, in order for DeepSleep configuration to take effect, the DeepSleep control bit has to be enabled. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 527f884d2d94981016e181dcbd4c4b5bf597c0ad. Reviewed-by: Dhruva Gole Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 13e1d36123d5..d3bed23134ca 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -249,7 +249,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */ + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; -- 2.34.1