From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 811B426F28F; Fri, 5 Sep 2025 05:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757049337; cv=none; b=lAbhPOc1YDS1i2an7WyHARyR4eOlbBAIKzmUs2GD5vLG3+ah+6bKrZig26xzubxgmvpq/sF3Cd1BmrEWhASiLUVQi0JckSc26aletB62UNqsvR3yjyWHKnxn4O/49VK15nDGxw1nJB4AvZPDZ/IUFOvh8YcGv1WW8tg9zRGh2yU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757049337; c=relaxed/simple; bh=Y4SfqZXT1zinII44LI4/ErYRVTagxJHZNVy3uwL5Vig=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QnC4UGs2npYl0fG6mGa29vLvxuFechfzQN++f9pfVDI5AUrv49aNP5LgbhXfVxW5B0j+x/bYe+nRpSDkDHfFf25Z8McLWaRd5/9FFlgxUnXNNu/wsYHeOxT/Wm+R+yxAE2U6UW4MV3JaF3f03w7BM1tDGbx2v41OVGGlvOrP6PA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ZBa7J4M2; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ZBa7J4M2" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5855FUB53636852; Fri, 5 Sep 2025 00:15:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757049330; bh=y8Kc2wMdyv6dOk92CCEM6wfNye3q/Jnonf7S+vWL8/I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZBa7J4M2ejmFH7jiza3xrJ+UnhAwePpeDJfAmthr8xMXhIDxGymZBTK7LznpXj05q D0eNDjY+/6Gl4bYTDxzgaKsQmLp9o7LEkjkKqmWJPFbN68vzoeYZaGfrQa3EYuBfca H14uWLCOa8mxkTzB695aO/hwnL/ai1z29MI1acJ0= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5855FUP6687115 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 5 Sep 2025 00:15:30 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 00:15:30 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 00:15:30 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5855Ep0i4118818; Fri, 5 Sep 2025 00:15:26 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , , , CC: Subject: [PATCH v5 4/4] arm64: dts: ti: k3-pinctrl: Fix the bug in existing macros Date: Fri, 5 Sep 2025 10:44:48 +0530 Message-ID: <20250905051448.2836237-5-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905051448.2836237-1-a-kaur@ti.com> References: <20250905051448.2836237-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Currently, DS_IO_OVERRIDE_EN_SHIFT macro is not defined anywhere but used for defining other macro. Replace this undefined macro with valid macro. Rename the existing macro to reflect the actual behavior. Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index 8ce37ace94c9..e46f7bf52701 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -88,8 +88,8 @@ #define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) #define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) -#define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT) -#define PIN_DS_IO_OVERRIDE_ENABLE (1 << DS_IO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_DISABLE (0 << ISO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_ENABLE (1 << ISO_OVERRIDE_EN_SHIFT) #define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) -- 2.34.1