[PATCH v1 0/4] Fix USB controller support for RK3368

[PATCH v1 0/4] Fix USB controller support for RK3368

[WeiHao Li]

This series fixs USB controller support for the Rockchip RK3368 SoC.

Key changes:
 - Update phy-rockchip-inno-usb2 driver to preperly handle RK3368 usb
   phy initialization and configuration.
 - Add usb PHY node to rk3368.dtsi with correct clocks and register
   mapping.
 - Add missing OHCI node, add missing attribute for usb host node.
 - Add dt-bindings document.

These changes were tested on a RK3368-based board [1]. Both of USB ports
can emumerate device (HID and mass storage).

Main code changes come from the rockchip downstream source [2].

[1] https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368
[2] https://github.com/rockchip-linux/kernel

Tested-by: WeiHao Li <cn.liweihao@gmail.com>
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>

WeiHao Li (4):
  phy: rockchip: inno-usb2: Add usb2 phy support for RK3368
  arm64: dts: rockchip: Add USB2.0 PHY for RK3368
  dt-bindings: phy: rockchip,inno-usb2phy: Document rk3368 usb phy
  arm64: dts: rockchip: Add phys attribute for USB host node

 .../bindings/phy/rockchip,inno-usb2phy.yaml   |  2 +
 arch/arm64/boot/dts/rockchip/rk3368.dtsi      | 47 +++++++++++++++++-
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 49 +++++++++++++++++++
 3 files changed, 96 insertions(+), 2 deletions(-)

-- 
2.39.5

[PATCH v1 1/4] phy: rockchip: inno-usb2: Add usb2 phy support for RK3368

[WeiHao Li]

RK3368 has one USB2.0 PHY with two ports. This adds device specific data
for it. Device specific data get form rockchip downstream source [1].

[1] https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/phy/rockchip/phy-rockchip-inno-usb2.c#L2805

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index b0f23690ec..c6c575bce9 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1847,6 +1847,54 @@ static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
 	{ /* sentinel */ }
 };
 
+static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = {
+	{
+		.reg = 0x700,
+		.num_ports	= 2,
+		.clkout_ctl	= { 0x0724, 15, 15, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0700, 8, 0, 0, 0x1d1 },
+				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
+				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
+				.bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
+				.idfall_det_en	= { 0x0680, 6, 6, 0, 1 },
+				.idfall_det_st	= { 0x0690, 6, 6, 0, 1 },
+				.idfall_det_clr	= { 0x06a0, 6, 6, 0, 1 },
+				.idrise_det_en	= { 0x0680, 5, 5, 0, 1 },
+				.idrise_det_st	= { 0x0690, 5, 5, 0, 1 },
+				.idrise_det_clr	= { 0x06a0, 5, 5, 0, 1 },
+				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
+				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
+				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
+				.utmi_bvalid	= { 0x04bc, 23, 23, 0, 1 },
+				.utmi_id	= { 0x04bc, 26, 26, 0, 1 },
+				.utmi_ls	= { 0x04bc, 25, 24, 0, 1 },
+				.ls_det_en	= { 0x079c, 15, 15, 1, 0 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x0728, 8, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
+				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
+				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
+			}
+		},
+		.chg_det = {
+			.opmode		= { 0x0700, 8, 0, 0, 0x1d7 },
+			.cp_det		= { 0x04b8, 30, 30, 0, 1 },
+			.dcp_det	= { 0x04b8, 29, 29, 0, 1 },
+			.dp_det		= { 0x04b8, 31, 31, 0, 1 },
+			.idm_sink_en	= { 0x0718, 8, 8, 0, 1 },
+			.idp_sink_en	= { 0x0718, 7, 7, 0, 1 },
+			.idp_src_en	= { 0x0718, 9, 9, 0, 1 },
+			.rdm_pdwn_en	= { 0x0718, 10, 10, 0, 1 },
+			.vdm_src_en	= { 0x0718, 12, 12, 0, 1 },
+			.vdp_src_en	= { 0x0718, 11, 11, 0, 1 },
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
 	{
 		.reg		= 0xe450,
@@ -2289,6 +2337,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = {
 	{ .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
 	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
+	{ .compatible = "rockchip,rk3368-usb2phy", .data = &rk3368_phy_cfgs },
 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
 	{ .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs },
 	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
-- 
2.39.5

[PATCH v1 2/4] arm64: dts: rockchip: Add USB2.0 PHY for RK3368

[WeiHao Li]

RK3368 has one USB2.0 PHY with two ports, This adds device tree node for
it.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 29 ++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 1b21787269..b09e431a64 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -766,11 +766,40 @@ cru: clock-controller@ff760000 {
 	grf: syscon@ff770000 {
 		compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xff770000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
 
 		io_domains: io-domains {
 			compatible = "rockchip,rk3368-io-voltage-domain";
 			status = "disabled";
 		};
+
+		u2phy: usb2-phy@700 {
+			compatible = "rockchip,rk3368-usb2phy";
+			reg = <0x700 0x2c>;
+			clocks = <&cru SCLK_OTGPHY0>;
+			clock-names = "phyclk";
+			clock-output-names = "usb480m_phy";
+			#clock-cells = <0>;
+			status = "disabled";
+
+			u2phy_otg: otg-port {
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "otg-bvalid", "otg-id",
+						  "linestate";
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
+			u2phy_host: host-port {
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
 	};
 
 	wdt: watchdog@ff800000 {
-- 
2.39.5

[PATCH v1 3/4] dt-bindings: phy: rockchip,inno-usb2phy: Document rk3368 usb phy

[WeiHao Li]

Add compatible for the USB2 phy in the Rockchip RK3368 SoC.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 .../devicetree/bindings/phy/rockchip,inno-usb2phy.yaml          | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
index 58e735b5dd..6e3197c168 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
@@ -19,6 +19,7 @@ properties:
       - rockchip,rk3308-usb2phy
       - rockchip,rk3328-usb2phy
       - rockchip,rk3366-usb2phy
+      - rockchip,rk3368-usb2phy
       - rockchip,rk3399-usb2phy
       - rockchip,rk3562-usb2phy
       - rockchip,rk3568-usb2phy
@@ -192,6 +193,7 @@ allOf:
               - rockchip,rk3308-usb2phy
               - rockchip,rk3328-usb2phy
               - rockchip,rk3366-usb2phy
+              - rockchip,rk3368-usb2phy
               - rockchip,rk3399-usb2phy
               - rockchip,rk3562-usb2phy
               - rockchip,rk3568-usb2phy
-- 
2.39.5

[PATCH v1 4/4] arm64: dts: rockchip: Add phys attribute of USB host node for RK3368

[WeiHao Li]

RK3368 has a USB host controller and a OTG controller, both of them use
a extra phy, this add missing ohci node and add phys attribute for them.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index b09e431a64..cdcbc0a944 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -503,9 +503,21 @@ gmac: ethernet@ff290000 {
 
 	usb_host0_ehci: usb@ff500000 {
 		compatible = "generic-ehci";
-		reg = <0x0 0xff500000 0x0 0x100>;
+		reg = <0x0 0xff500000 0x0 0x20000>;
 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_HOST0>;
+		clocks = <&cru HCLK_HOST0>, <&u2phy>;
+		phys = <&u2phy_host>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_host0_ohci: usb@ff520000 {
+		compatible = "generic-ohci";
+		reg = <0x0 0xff520000 0x0 0x20000>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST0>, <&u2phy>;
+		phys = <&u2phy_host>;
+		phy-names = "usb";
 		status = "disabled";
 	};
 
@@ -520,6 +532,8 @@ usb_otg: usb@ff580000 {
 		g-np-tx-fifo-size = <16>;
 		g-rx-fifo-size = <275>;
 		g-tx-fifo-size = <256 128 128 64 64 32>;
+		phys = <&u2phy_otg>;
+		phy-names = "usb2-phy";
 		status = "disabled";
 	};
 
-- 
2.39.5

Re: [PATCH v1 3/4] dt-bindings: phy: rockchip,inno-usb2phy: Document rk3368 usb phy

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 52 bytes --]

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v1 1/4] phy: rockchip: inno-usb2: Add usb2 phy support for RK3368

[kernel test robot]

Hi WeiHao,

kernel test robot noticed the following build warnings:

[auto build test WARNING on rockchip/for-next]
[also build test WARNING on robh/for-next arm/for-next arm/fixes arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next linus/master v6.17-rc4 next-20250905]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/WeiHao-Li/phy-rockchip-inno-usb2-Add-usb2-phy-support-for-RK3368/20250905-205804
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
patch link:    https://lore.kernel.org/r/20250905125318.7956-2-cn.liweihao%40gmail.com
patch subject: [PATCH v1 1/4] phy: rockchip: inno-usb2: Add usb2 phy support for RK3368
config: arc-randconfig-r132-20250907 (https://download.01.org/0day-ci/archive/20250907/202509072227.wBI6dBl4-lkp@intel.com/config)
compiler: arc-linux-gcc (GCC) 15.1.0
reproduce: (https://download.01.org/0day-ci/archive/20250907/202509072227.wBI6dBl4-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509072227.wBI6dBl4-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1867:34: sparse: sparse: Initializer entry defined twice
   drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1873:34: sparse:   also defined here

vim +1867 drivers/phy/rockchip/phy-rockchip-inno-usb2.c

  1849	
  1850	static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = {
  1851		{
  1852			.reg = 0x700,
  1853			.num_ports	= 2,
  1854			.clkout_ctl	= { 0x0724, 15, 15, 1, 0 },
  1855			.port_cfgs	= {
  1856				[USB2PHY_PORT_OTG] = {
  1857					.phy_sus	= { 0x0700, 8, 0, 0, 0x1d1 },
  1858					.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
  1859					.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
  1860					.bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
  1861					.idfall_det_en	= { 0x0680, 6, 6, 0, 1 },
  1862					.idfall_det_st	= { 0x0690, 6, 6, 0, 1 },
  1863					.idfall_det_clr	= { 0x06a0, 6, 6, 0, 1 },
  1864					.idrise_det_en	= { 0x0680, 5, 5, 0, 1 },
  1865					.idrise_det_st	= { 0x0690, 5, 5, 0, 1 },
  1866					.idrise_det_clr	= { 0x06a0, 5, 5, 0, 1 },
> 1867					.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
  1868					.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
  1869					.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
  1870					.utmi_bvalid	= { 0x04bc, 23, 23, 0, 1 },
  1871					.utmi_id	= { 0x04bc, 26, 26, 0, 1 },
  1872					.utmi_ls	= { 0x04bc, 25, 24, 0, 1 },
  1873					.ls_det_en	= { 0x079c, 15, 15, 1, 0 },
  1874				},
  1875				[USB2PHY_PORT_HOST] = {
  1876					.phy_sus	= { 0x0728, 8, 0, 0, 0x1d1 },
  1877					.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
  1878					.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
  1879					.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
  1880				}
  1881			},
  1882			.chg_det = {
  1883				.opmode		= { 0x0700, 8, 0, 0, 0x1d7 },
  1884				.cp_det		= { 0x04b8, 30, 30, 0, 1 },
  1885				.dcp_det	= { 0x04b8, 29, 29, 0, 1 },
  1886				.dp_det		= { 0x04b8, 31, 31, 0, 1 },
  1887				.idm_sink_en	= { 0x0718, 8, 8, 0, 1 },
  1888				.idp_sink_en	= { 0x0718, 7, 7, 0, 1 },
  1889				.idp_src_en	= { 0x0718, 9, 9, 0, 1 },
  1890				.rdm_pdwn_en	= { 0x0718, 10, 10, 0, 1 },
  1891				.vdm_src_en	= { 0x0718, 12, 12, 0, 1 },
  1892				.vdp_src_en	= { 0x0718, 11, 11, 0, 1 },
  1893			},
  1894		},
  1895		{ /* sentinel */ }
  1896	};
  1897	

-- 
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https://github.com/intel/lkp-tests/wiki