From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
Jinlong Mao <jinlong.mao@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, Jie Gan <jie.gan@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH v6 9/9] arm64: dts: qcom: lemans: Add interrupts to CTCU device
Date: Mon, 08 Sep 2025 10:02:01 +0800 [thread overview]
Message-ID: <20250908-enable-byte-cntr-for-tmc-v6-9-1db9e621441a@oss.qualcomm.com> (raw)
In-Reply-To: <20250908-enable-byte-cntr-for-tmc-v6-0-1db9e621441a@oss.qualcomm.com>
Add interrupts to enable byte-cntr function for TMC ETR devices.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index f5ec60086d60..0a17a26f85a5 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -2774,6 +2774,11 @@ ctcu@4001000 {
clocks = <&aoss_qmp>;
clock-names = "apb";
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "etr0",
+ "etr1";
+
in-ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.34.1
prev parent reply other threads:[~2025-09-08 2:03 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 2:01 [PATCH v6 0/9] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-09-08 2:01 ` [PATCH v6 1/9] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-12-03 16:18 ` Suzuki K Poulose
2025-12-04 2:45 ` Jie Gan
2025-09-08 2:01 ` [PATCH v6 2/9] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-12-03 16:15 ` Suzuki K Poulose
2025-12-04 2:47 ` Jie Gan
2025-09-08 2:01 ` [PATCH v6 3/9] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-12-03 14:24 ` Mike Leach
2025-12-03 16:20 ` Suzuki K Poulose
2025-09-08 2:01 ` [PATCH v6 4/9] coresight: tmc: add create/clean functions for etr_buf_list Jie Gan
2025-12-03 14:26 ` Mike Leach
2025-09-08 2:01 ` [PATCH v6 5/9] coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations Jie Gan
2025-09-08 2:01 ` [PATCH v6 6/9] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-12-03 14:30 ` Mike Leach
2025-12-04 2:49 ` Jie Gan
2025-12-03 18:14 ` Suzuki K Poulose
2025-12-04 2:53 ` Jie Gan
2025-12-04 9:22 ` Suzuki K Poulose
2025-12-05 1:01 ` Jie Gan
2025-09-08 2:01 ` [PATCH v6 7/9] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-09-08 2:02 ` [PATCH v6 8/9] coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops Jie Gan
2025-09-08 2:02 ` Jie Gan [this message]
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