From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [13.76.142.27]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 15389146585; Mon, 15 Sep 2025 13:00:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.76.142.27 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757941216; cv=none; b=HabJNw6QgMAcFmrUNq8VRab95g4Dy+HFDqxNJ4XGwbPxqz7fkLYo/Jl0ijkCpQ21O7CDFhg176lNfDg4MSBn/MLfec4Z5YdjOlBkod94J5zqPR9p/t9zEaQeR0XvE6UtIXLrr0xPK8apYqYDrRcnsU4yoWpWcueN1A+U9LygoUM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757941216; c=relaxed/simple; bh=mDbOBD+3FuF601bHAG1CHaG87o37JmqxmO1yeYTlTgU=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=W/eKwm+5APOjcsw+JU/kyElgiyLZN6sqeQSWtKmoUe6B95u6B6rks5my7k/u9TDLEngDFrCz6lBD8PX6p9LEEPYZ0EbJbyxnCLFGaa3WYvDjJXQN0FZrCuulg6RyNKmhHwFcrMtct/ptIGgtNUS5STa1fK4aLH4SmHK2+MltoZE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=13.76.142.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0006800LT.eswin.cn (unknown [10.12.96.77]) by app1 (Coremail) with SMTP id TAJkCgAHHxDLDchoKHHRAA--.49807S2; Mon, 15 Sep 2025 20:59:57 +0800 (CST) From: Yulin Lu To: dlemoal@kernel.org, cassel@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, linux-phy@lists.infradead.org Cc: ningyu@eswincomputing.com, zhengyu@eswincomputing.com, linmin@eswincomputing.com, huangyifeng@eswincomputing.com, fenglin@eswincomputing.com, lianghujun@eswincomputing.com, Yulin Lu Subject: [PATCH v4 0/3] Add driver support for Eswin EIC7700 SoC SATA Controller and PHY Date: Mon, 15 Sep 2025 20:59:02 +0800 Message-Id: <20250915125902.375-1-luyulin@eswincomputing.com> X-Mailer: git-send-email 2.31.1.windows.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:TAJkCgAHHxDLDchoKHHRAA--.49807S2 X-Coremail-Antispam: 1UD129KBjvJXoWxZF4DtF1ktFWfWryxCrykZrb_yoWrtw4kpa ykCry2yrn5tryxta97Ja1I9a4Svan7GFW3urs3Jw1UZwsxXFyvvwsak3WYvFykCw4kKryY qF4aqFy5CFyUAFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9l14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628v n2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I 8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AK xVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcV AFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8I cIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r 4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRNJ5oDUUUU X-CM-SenderInfo: pox13z1lq6v25zlqu0xpsx3x1qjou0bp/ This series depends on the config option patch [1]. [1] https://lore.kernel.org/all/20250825132427.1618089-3-pinkesh.vaghela@einfochips.com/ Updates: v4 -> v3: - eswin,eic7700-ahci.yaml - Fix grammatical errors in patch subject and commit message - Add an explanation in the commit message of patch 1 for retaining the "ports-implemented" field, which Rob Herring suggested to remove in the review comments on v2. Link to Rob Herring's review: https://lore.kernel.org/lkml/CAL_JsqKFotNLZZXwiy7S6K8qXLdGRAnsa-1zvZRDQBE39Gf5kg@mail.gmail.com/ Link to my question and Niklas Cassel's reply: https://lore.kernel.org/lkml/aLBUC116MdJqDGIJ@flawful.org/ In this reply, Niklas Cassel mentioned his view: If the ports-implemented register gets reset from ahci_platform_assert_rsts(), then it seems acceptable to retain the ports-implemented property in the device tree. This aligns with our design. Link to my reply: https://lore.kernel.org/lkml/4ab70c6a.8be.198f47da494.Coremail.luyulin@eswincomputing.com/ Link to Niklas Cassel's question and my further explanation: https://lore.kernel.org/lkml/aLlYkZWBaI5Yz6fo@ryzen/ https://lore.kernel.org/lkml/7206383a.d98.19918c22570.Coremail.luyulin@eswincomputing.com/ - eswin,eic7700-sata-phy.yaml - Fix grammatical errors in patch subject and commit message - Adjust the position of reg in the properties and required arrays - Add reviewed-by tag of Krzysztof Kozlowski - phy-eic7700-sata.c - Correct the loop condition in wait_for_phy_ready() to use the current jiffies instead of the fixed start time - Change the return value from -EFAULT to -ETIMEDOUT to correctly indicate a timeout condition - Remove redundant clock disable handling in probe error path, as SATA_SYS_CLK_EN is managed in phy_init() and phy_exit() - Use dev_err_probe return in probe - Reorder local variables to follow reverse Xmas tree order - Wrap each line in the extended comments to 80 columns before splitting lines - Adjust the position of `#include ` for proper ordering - Link to v3: https://lore.kernel.org/lkml/20250904063427.1954-1-luyulin@eswincomputing.com/ v2 -> v3: - Use full name in "From" and "Signed-off-by" fields information - eswin,eic7700-ahci.yaml - Remove the introduction to the reg, interrupts, phys, and phy-names fields - Modify the usage of the clocks field in the examples - Correct the order of dt properties - phy-eic7700-sata.c - Register operations use the GENMASK macro and FIELD_PREP instead of the original bit offset method, and add "#include " - Modify some macro definition names. - Remove the redundant initialization assignments for "ret" and "val" - Delete ".suppress_bind_attrs = true" - Modify the driver name - Add "#include " to fix the robot test issue - Link to v2: https://lore.kernel.org/lkml/20250819134722.220-1-luyulin@eswincomputing.com/ v2 -> v1: - Delete the original controller driver and use ahci_dwc.c instead - Add eswin,eic7700-ahci.yaml - Correct the descriptions of reset, interrupt and other hardware resources for the sata controller on EIC7700 SoC - The clocks for both sata controller and sata PHY are controlled via a register bit in the HSP bus and are not registered in the clock tree. Clock are managed within the PHY driver, therefore it is not described in this document - Add $ref: snps,dwc-ahci-common.yaml#. - Add eswin,eic7700-sata-phy.yaml - Add this file to include the description of the PHY on EIC7700 SoC - Add an eswin directory under the PHY driver path, and include the SATA PHY driver code for EIC7700 SoC - Link to v1: https://lore.kernel.org/all/20250515085114.1692-1-hehuan1@eswincomputing.com/ Yulin Lu (3): Document the EIC7700 SoC sata ahci dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver .../bindings/ata/eswin,eic7700-ahci.yaml | 79 +++++++ .../bindings/phy/eswin,eic7700-sata-phy.yaml | 36 ++++ drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/eswin/Kconfig | 14 ++ drivers/phy/eswin/Makefile | 2 + drivers/phy/eswin/phy-eic7700-sata.c | 192 ++++++++++++++++++ 7 files changed, 325 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml create mode 100644 drivers/phy/eswin/Kconfig create mode 100644 drivers/phy/eswin/Makefile create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c -- 2.25.1