[PATCH v3 00/10] drivers: gpio: and the QIXIS FPGA GPIO controller

[PATCH v3 00/10] drivers: gpio: and the QIXIS FPGA GPIO controller

[Ioana Ciornei]

This patch set adds support for the GPIO controllers on the QIXIS FPGAs
found on some Layerscape boards such as LX2160ARDB and LS1046AQDS. At
the same time it describes the SFP+ cages found on these boards, which
are the users of those GPIO lines.

Before actually adding the GPIO driver, patches #2 and #3 add and
describe a new compatible string - fsl,lx2160ardb-fpga - which would be
used for the QIXIS FPGA found on the LX2160ARDB board. As opposed to the
other compatible strings found in fsl,fpga-qixis-i2c.yaml, the
fsl,lx2160ardb-fpga imposes a unit address for its child devices. This
will be used in the next patches when the gpio controller node will
define its unit address as the address of its underlying register offset
inside the FPGA. This requirement is described in the yaml file and it
only affects the newly added compatible.

Moving on to the GPIO subsystem, patch #4 is extending the gpio-regmap
with the fixed_direction_output bitmap which could be used by user
drivers to transmit directly the fixed direction of all the GPIO lines.

Even though this patch set touches multiple subsytems, each with their
own tree, I submit everything at once so that we can have a clear
picture on the overall intention. The hope is that each subsystem can
pick up the related patches since there is no compile time dependency
between them.

Please note that CHECK_DTBS will fail without the following fixup patch.
https://lore.kernel.org/all/20250912165916.3098215-1-ioana.ciornei@nxp.com/

Changes in v2:
- 1/9: Used the newly added trivial-gpio.yaml file
- 1/9: Removed redundant "bindings" from commit title
- 1/9: Added only one compatible string for the gpio controllers on
  LX2160ARDB since both registers have the same layout.
- 2/9: Enforce a unit address on the child gpios nodes (remove the ?)
- 2/9: Enforce the use of unit addresses by having #address-size and
  #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
- 4/9: Add the fixed_direction_output bitmap to the gpio_regmap_config
- 5/9: Use the newly added .fixed_direction_output bitmap
  representing the fixed direction of the GPIO lines.
- 6/9: Use the same compatible string for both GPIO controller nodes.

Changes in v3:
- 2/10: Replace the trivial-gpio reference with an explicit mention of
  the accepted child gpio compatible.
- 2/10: Reword the commit message.
- 2/10: Add the 'else' case to the if statement.
- 3/10: New patch
- 5/10: Make a deep copy of the new bitmap.
- 5/10: Remove the offset check against the ngpio.
- 5/10: Added documentation for the new config field.
- 6/10: Remove 'drivers' from the commit title.
- 6/10: Remove the qixis_cpld_gpio_type enum since its not needed.
- 6/10: Remove the NULL check for device_get_match_data().
- 6/10: Use a bitmap declared on the stack as the config field passed to
  gpio-regmap.
- 9,10/10: Moved the reg property before address/cells-size.

Ioana Ciornei (10):
  dt-bindings: gpio: add QIXIS FPGA based GPIO controller
  dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA
  dt-bindings: fsl,fpga-qixis: describe the gpio child node found on
    LS1046AQDS
  mfd: simple-mfd-i2c: add compatible string for LX2160ARDB
  gpio: regmap: add the .fixed_direction_output configuration parameter
  gpio: add QIXIS FPGA GPIO controller
  arm64: dts: lx2160a-rdb: describe the QIXIS FPGA and two child GPIO
    controllers
  arm64: dts: ls1046a-qds: describe the FPGA based GPIO controller
  arm64: dts: lx2160a-rdb: fully describe the two SFP+ cages
  arm64: dts: ls1046a-qds: describe the two on-board SFP+ cages

 .../bindings/board/fsl,fpga-qixis-i2c.yaml    |  58 ++++++++++
 .../bindings/board/fsl,fpga-qixis.yaml        |  10 ++
 .../bindings/gpio/trivial-gpio.yaml           |   2 +
 .../boot/dts/freescale/fsl-ls1046a-qds.dts    |  52 +++++++++
 .../boot/dts/freescale/fsl-lx2160a-rdb.dts    |  78 +++++++++++++
 drivers/gpio/Kconfig                          |   9 ++
 drivers/gpio/Makefile                         |   1 +
 drivers/gpio/gpio-qixis-fpga.c                | 107 ++++++++++++++++++
 drivers/gpio/gpio-regmap.c                    |  18 +++
 drivers/mfd/simple-mfd-i2c.c                  |   1 +
 include/linux/gpio/regmap.h                   |   6 +
 11 files changed, 342 insertions(+)
 create mode 100644 drivers/gpio/gpio-qixis-fpga.c

-- 
2.25.1

[PATCH v3 01/10] dt-bindings: gpio: add QIXIS FPGA based GPIO controller

[Ioana Ciornei]

Add a device tree binding for the QIXIS FPGA based GPIO controller.
Depending on the board, the QIXIS FPGA exposes registers which act as a
GPIO controller, each with 8 GPIO lines of fixed direction.

Since each QIXIS FPGA layout has its particularities, add a separate
compatible string for each board/GPIO register combination supported.

Since these GPIO controllers are trivial, make use of the newly added
trivial-gpio.yaml file instead of creating an entirely new one.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
Changes in v2:
- Used the newly added trivial-gpio.yaml file
- Removed redundant "bindings" from commit title
- Added only one compatible string for the gpio controllers on
  LX2160ARDB since both registers have the same layout.
Changes in v3:
- none

 Documentation/devicetree/bindings/gpio/trivial-gpio.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
index c994177de940..3f4bbd57fc52 100644
--- a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
@@ -22,6 +22,8 @@ properties:
           - cznic,moxtet-gpio
           - dlg,slg7xl45106
           - fcs,fxl6408
+          - fsl,ls1046aqds-fpga-gpio-stat-pres2
+          - fsl,lx2160ardb-fpga-gpio-sfp
           - gateworks,pld-gpio
           - ibm,ppc4xx-gpio
           - loongson,ls1x-gpio
-- 
2.25.1

[PATCH v3 02/10] dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA

[Ioana Ciornei]

Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.

Since the register map exposed by the LX2160ARDB's FPGA also contains
two GPIO controllers, accept the necessary GPIO pattern property.
At the same time, add the #address-cells and #size-cells properties as
valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
addressable.

This is necessary because when defining child devices such as the GPIO
controller described in the added example, the child device needs a the
reg property to properly identify its register location in the parent
I2C device address space.

Impose this restriction for the new compatible through an if-statement.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Enforce a unit address on the child gpios nodes (remove the ?)
- Enforce the use of unit addresses by having #address-size and
  #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
Changes in v3:
- Replace the trivial-gpio reference with an explicit mention of the
  accepted child gpio compatible.
- Reword the commit message.
- Add the 'else' case to the if statement.

 .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
index 28b37772fb65..e889dac052e7 100644
--- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
+++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
@@ -22,6 +22,13 @@ properties:
               - fsl,lx2160aqds-fpga
           - const: fsl,fpga-qixis-i2c
           - const: simple-mfd
+      - const: fsl,lx2160ardb-fpga
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
 
   interrupts:
     maxItems: 1
@@ -32,10 +39,37 @@ properties:
   mux-controller:
     $ref: /schemas/mux/reg-mux.yaml
 
+patternProperties:
+  "^gpio@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        contains:
+          enum:
+            - fsl,lx2160ardb-fpga-gpio-sfp
+
 required:
   - compatible
   - reg
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - fsl,lx2160ardb-fpga
+    then:
+      required:
+        - "#address-cells"
+        - "#size-cells"
+    else:
+      properties:
+        "#address-cells": false
+        "#size-cells": false
+
 additionalProperties: false
 
 examples:
@@ -68,3 +102,27 @@ examples:
         };
     };
 
+  - |
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        board-control@66 {
+            compatible = "fsl,lx2160ardb-fpga";
+            reg = <0x66>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            gpio@19 {
+                compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
+                reg = <0x19>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                gpio-line-names =
+                    "SFP2_TX_EN", "",
+                    "", "",
+                    "SFP2_RX_LOS", "SFP2_TX_FAULT",
+                    "", "SFP2_MOD_ABS";
+            };
+        };
+    };
-- 
2.25.1

[PATCH v3 03/10] dt-bindings: fsl,fpga-qixis: describe the gpio child node found on LS1046AQDS

[Ioana Ciornei]

Extend the list of accepted child nodes with the QIXIS FPGA based GPIO
controller and explicitly list its compatible string
fsl,ls1046aqds-fpga-gpio-stat-pres2 as the only one accepted.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v3:
- new patch

 .../devicetree/bindings/board/fsl,fpga-qixis.yaml      | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml
index 5a3cd431ef6e..2eacb581b9fd 100644
--- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml
+++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml
@@ -57,6 +57,16 @@ patternProperties:
   '^mdio-mux@[a-f0-9,]+$':
     $ref: /schemas/net/mdio-mux-mmioreg.yaml
 
+  '^gpio@[0-9a-f]+$':
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        contains:
+          enum:
+            - fsl,ls1046aqds-fpga-gpio-stat-pres2
+
 required:
   - compatible
   - reg
-- 
2.25.1

[PATCH v3 04/10] mfd: simple-mfd-i2c: add compatible string for LX2160ARDB

[Ioana Ciornei]

Extend the list of supported devices with the QIXIS FPGA found on the
LX2160ARDB board.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
Changes in v3:
- none

 drivers/mfd/simple-mfd-i2c.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c
index 63ac26388860..6fbe85437d8d 100644
--- a/drivers/mfd/simple-mfd-i2c.c
+++ b/drivers/mfd/simple-mfd-i2c.c
@@ -115,6 +115,7 @@ static const struct of_device_id simple_mfd_i2c_of_match[] = {
 	{ .compatible = "maxim,max5970", .data = &maxim_max5970},
 	{ .compatible = "maxim,max5978", .data = &maxim_max5970},
 	{ .compatible = "maxim,max77705-battery", .data = &maxim_mon_max77705},
+	{ .compatible = "fsl,lx2160ardb-fpga" },
 	{ .compatible = "fsl,lx2160aqds-fpga" },
 	{ .compatible = "fsl,ls1028aqds-fpga" },
 	{ .compatible = "spacemit,p1", .data = &spacemit_p1, },
-- 
2.25.1

[PATCH v3 05/10] gpio: regmap: add the .fixed_direction_output configuration parameter

[Ioana Ciornei]

There are GPIO controllers such as the one present in the LX2160ARDB
QIXIS FPGA which have fixed-direction input and output GPIO lines mixed
together in a single register. This cannot be modeled using the
gpio-regmap as-is since there is no way to present the true direction of
a GPIO line.

In order to make this use case possible, add a new configuration
parameter - fixed_direction_output - into the gpio_regmap_config
structure. This will enable user drivers to provide a bitmap that
represents the fixed direction of the GPIO lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Add the fixed_direction_output bitmap to the gpio_regmap_config
Changes in v3:
- Make a deep copy of the new bitmap.
- Remove the offset check against the ngpio.
- Added documentation for the new config field.

 drivers/gpio/gpio-regmap.c  | 18 ++++++++++++++++++
 include/linux/gpio/regmap.h |  6 ++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
index e8a32dfebdcb..9edd79b5c10e 100644
--- a/drivers/gpio/gpio-regmap.c
+++ b/drivers/gpio/gpio-regmap.c
@@ -31,6 +31,7 @@ struct gpio_regmap {
 	unsigned int reg_clr_base;
 	unsigned int reg_dir_in_base;
 	unsigned int reg_dir_out_base;
+	unsigned long *fixed_direction_output;
 
 	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
 			      unsigned int offset, unsigned int *reg,
@@ -129,6 +130,13 @@ static int gpio_regmap_get_direction(struct gpio_chip *chip,
 	unsigned int base, val, reg, mask;
 	int invert, ret;
 
+	if (gpio->fixed_direction_output) {
+		if (test_bit(offset, gpio->fixed_direction_output))
+			return GPIO_LINE_DIRECTION_OUT;
+		else
+			return GPIO_LINE_DIRECTION_IN;
+	}
+
 	if (gpio->reg_dat_base && !gpio->reg_set_base)
 		return GPIO_LINE_DIRECTION_IN;
 	if (gpio->reg_set_base && !gpio->reg_dat_base)
@@ -277,6 +285,16 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config
 			return ERR_PTR(ret);
 	}
 
+	if (config->fixed_direction_output) {
+		gpio->fixed_direction_output = devm_bitmap_alloc(config->parent,
+								 chip->ngpio,
+								 GFP_KERNEL);
+		if (!gpio->fixed_direction_output)
+			return ERR_PTR(-ENOMEM);
+		bitmap_copy(gpio->fixed_direction_output,
+			    config->fixed_direction_output, chip->ngpio);
+	}
+
 	/* if not set, assume there is only one register */
 	gpio->ngpio_per_reg = config->ngpio_per_reg;
 	if (!gpio->ngpio_per_reg)
diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h
index c722c67668c6..8d3d595bfdd3 100644
--- a/include/linux/gpio/regmap.h
+++ b/include/linux/gpio/regmap.h
@@ -37,6 +37,10 @@ struct regmap;
  *			offset to a register/bitmask pair. If not
  *			given the default gpio_regmap_simple_xlate()
  *			is used.
+ * @fixed_direction_output:
+ *			(Optional) Bitmap representing the fixed direction of
+ *			the GPIO lines. Useful when there are GPIO lines with a
+ *			fixed direction mixed together in the same register.
  * @drvdata:		(Optional) Pointer to driver specific data which is
  *			not used by gpio-remap but is provided "as is" to the
  *			driver callback(s).
@@ -78,6 +82,8 @@ struct gpio_regmap_config {
 	int ngpio_per_reg;
 	struct irq_domain *irq_domain;
 
+	unsigned long *fixed_direction_output;
+
 	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
 			      unsigned int offset, unsigned int *reg,
 			      unsigned int *mask);
-- 
2.25.1

[PATCH v3 06/10] gpio: add QIXIS FPGA GPIO controller

[Ioana Ciornei]

Add support for the GPIO controller found on some QIXIS FPGAs in
Layerscape boards such as LX2160ARDB and LS1046AQDS. This driver is
using gpio-regmap.

A GPIO controller has a maximum of 8 lines (all found in the same
register). Even within the same controller, the GPIO lines' direction is
fixed, which mean that both input and output lines are found in the same
register. This is why the driver also passed to gpio-regmap the newly
added .fixed_direction_output bitmap to represent the true direction of
the lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Use the newly added .fixed_direction_output bitmap representing
  the fixed direction of the GPIO lines.
Changes in v3:
- Remove 'drivers' from the commit title.
- Remove the qixis_cpld_gpio_type enum since its not needed.
- Remove the NULL check for device_get_match_data().
- Use a bitmap declared on the stack as the config field passed to
  gpio-regmap.

 drivers/gpio/Kconfig           |   9 +++
 drivers/gpio/Makefile          |   1 +
 drivers/gpio/gpio-qixis-fpga.c | 107 +++++++++++++++++++++++++++++++++
 3 files changed, 117 insertions(+)
 create mode 100644 drivers/gpio/gpio-qixis-fpga.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 81fe3b085f7b..e963a7ee4ce1 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1962,6 +1962,15 @@ config GPIO_LATCH
 	  Say yes here to enable a driver for GPIO multiplexers based on latches
 	  connected to other GPIOs.
 
+config GPIO_QIXIS_FPGA
+	tristate "NXP QIXIS FPGA GPIO support"
+	depends on MFD_SIMPLE_MFD_I2C || COMPILE_TEST
+	select GPIO_REGMAP
+	help
+	  This enables support for the GPIOs found in the QIXIS FPGA which is
+	  integrated on some NXP Layerscape boards such as LX2160ARDB and
+	  LS1046AQDS.
+
 config GPIO_MOCKUP
 	tristate "GPIO Testing Driver (DEPRECATED)"
 	select IRQ_SIM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index b1593ce92ebe..850c0e086c82 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -144,6 +144,7 @@ obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.o
 obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
 obj-$(CONFIG_GPIO_POLARFIRE_SOC)	+= gpio-mpfs.o
 obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
+obj-$(CONFIG_GPIO_QIXIS_FPGA)		+= gpio-qixis-fpga.o
 obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
 obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
 obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
diff --git a/drivers/gpio/gpio-qixis-fpga.c b/drivers/gpio/gpio-qixis-fpga.c
new file mode 100644
index 000000000000..048a2cac4f0f
--- /dev/null
+++ b/drivers/gpio/gpio-qixis-fpga.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Layerscape GPIO QIXIS FPGA driver
+ *
+ * Copyright 2025 NXP
+ */
+
+#include <linux/device.h>
+#include <linux/gpio/driver.h>
+#include <linux/gpio/regmap.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+struct qixis_cpld_gpio_config {
+	u64 output_lines;
+};
+
+static const struct qixis_cpld_gpio_config lx2160ardb_sfp_cfg = {
+	.output_lines = BIT(0),
+};
+
+static const struct qixis_cpld_gpio_config ls1046aqds_stat_pres2_cfg = {
+	.output_lines = 0x0,
+};
+
+static const struct regmap_config regmap_config_8r_8v = {
+	.reg_bits = 8,
+	.val_bits = 8,
+};
+
+static int qixis_cpld_gpio_probe(struct platform_device *pdev)
+{
+	DECLARE_BITMAP(fixed_direction_output, 8);
+	const struct qixis_cpld_gpio_config *cfg;
+	struct gpio_regmap_config config = {0};
+	struct regmap *regmap;
+	void __iomem *reg;
+	u32 base;
+	int ret;
+
+	if (!pdev->dev.parent)
+		return -ENODEV;
+
+	cfg = device_get_match_data(&pdev->dev);
+
+	ret = device_property_read_u32(&pdev->dev, "reg", &base);
+	if (ret)
+		return ret;
+
+	regmap = dev_get_regmap(pdev->dev.parent, NULL);
+	if (!regmap) {
+		/* In case there is no regmap configured by the parent device,
+		 * create our own from the MMIO space.
+		 */
+		reg = devm_platform_ioremap_resource(pdev, 0);
+		if (!reg)
+			return -ENODEV;
+
+		regmap = devm_regmap_init_mmio(&pdev->dev, reg, &regmap_config_8r_8v);
+		if (!regmap)
+			return -ENODEV;
+
+		/* In this case, the offset of our register is 0 inside the
+		 * regmap area that we just created.
+		 */
+		base = 0;
+	}
+	config.reg_dat_base = GPIO_REGMAP_ADDR(base);
+	config.reg_set_base = GPIO_REGMAP_ADDR(base);
+
+	config.drvdata = (void *)cfg;
+	config.regmap = regmap;
+	config.parent = &pdev->dev;
+	config.ngpio_per_reg = 8;
+	config.ngpio = 8;
+
+	bitmap_from_u64(fixed_direction_output, cfg->output_lines);
+	config.fixed_direction_output = fixed_direction_output;
+
+	return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config));
+}
+
+static const struct of_device_id qixis_cpld_gpio_of_match[] = {
+	{
+		.compatible = "fsl,lx2160ardb-fpga-gpio-sfp",
+		.data = &lx2160ardb_sfp_cfg,
+	},
+	{
+		.compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2",
+		.data = &ls1046aqds_stat_pres2_cfg,
+	},
+
+	{}
+};
+MODULE_DEVICE_TABLE(of, qixis_cpld_gpio_of_match);
+
+static struct platform_driver qixis_cpld_gpio_driver = {
+	.probe = qixis_cpld_gpio_probe,
+	.driver = {
+		.name = "gpio-qixis-cpld",
+		.of_match_table = qixis_cpld_gpio_of_match,
+	},
+};
+module_platform_driver(qixis_cpld_gpio_driver);
-- 
2.25.1

[PATCH v3 07/10] arm64: dts: lx2160a-rdb: describe the QIXIS FPGA and two child GPIO controllers

[Ioana Ciornei]

Describe the FPGA present on the LX2160ARDB board as a simple-mfd I2C
device. The FPGA presents registers that deal with power-on-reset
timing, muxing, SFP cage monitoring and control etc.

Also add the two GPIO controllers responsible for monitoring and
controlling the SFP+ cages used for MAC5 and MAC6.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
Changes in v2:
- Use the same compatible string for both GPIO controller nodes.
Changes in v3:
- none

 .../boot/dts/freescale/fsl-lx2160a-rdb.dts    | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 0c44b3cbef77..4ede1295f29d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -170,6 +170,37 @@ mt35xu512aba1: flash@1 {
 &i2c0 {
 	status = "okay";
 
+	cpld@66 {
+		compatible = "fsl,lx2160ardb-fpga";
+		reg = <0x66>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sfp2_csr: gpio@19 {
+			compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
+			reg = <0x19>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-line-names =
+				"SFP2_TX_EN", "",
+				"", "",
+				"SFP2_RX_LOS", "SFP2_TX_FAULT",
+				"", "SFP2_MOD_ABS";
+		};
+
+		sfp3_csr: gpio@1a {
+			compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
+			reg = <0x1a>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-line-names =
+				"SFP3_TX_EN", "",
+				"", "",
+				"SFP3_RX_LOS", "SFP3_TX_FAULT",
+				"", "SFP3_MOD_ABS";
+		};
+	};
+
 	i2c-mux@77 {
 		compatible = "nxp,pca9547";
 		reg = <0x77>;
-- 
2.25.1

[PATCH v3 08/10] arm64: dts: ls1046a-qds: describe the FPGA based GPIO controller

[Ioana Ciornei]

The QIXIS FPGA node is extended so that it describes the GPIO controller
responsible for all the status presence lines on both SFP+ cages as well
as the IO SLOTs present on the board.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
Changes in v2:
- none
Changes in v3:
- none

 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index 736722b58e77..812cf1c5d7f4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -166,8 +166,20 @@ nand@1,0 {
 
 	fpga: board-control@2,0 {
 		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
+		#address-cells = <1>;
+		#size-cells = <1>;
 		reg = <0x2 0x0 0x0000100>;
 		ranges = <0 2 0 0x100>;
+
+		stat_pres2: gpio@c {
+			compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2";
+			reg = <0xc 1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-line-names =
+				"SLOT1", "SLOT2", "SLOT3", "SLOT4", "SLOT5", "SLOT6",
+				"SFP1_MOD_DEF", "SFP2_MOD_DEF";
+		};
 	};
 };
 
-- 
2.25.1

[PATCH v3 09/10] arm64: dts: lx2160a-rdb: fully describe the two SFP+ cages

[Ioana Ciornei]

Describe the two SFP+ cages found on the LX2160ARDB board with their
respective I2C buses and GPIO lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
Changes in v3:
- Moved the reg property before address/cells-size.

 .../boot/dts/freescale/fsl-lx2160a-rdb.dts    | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 4ede1295f29d..1c1ed0c5f016 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -31,6 +31,28 @@ sb_3v3: regulator-sb3v3 {
 		regulator-boot-on;
 		regulator-always-on;
 	};
+
+	sfp2: sfp-2 {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfp2_i2c>;
+		maximum-power-milliwatt = <2000>;
+		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
+		/* tx-disable-gpios = <&sfp2_csr 0 GPIO_ACTIVE_HIGH>; */
+		los-gpios = <&sfp2_csr 4 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&sfp2_csr 5 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sfp2_csr 7 GPIO_ACTIVE_LOW>;
+	};
+
+	sfp3: sfp-3 {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfp3_i2c>;
+		maximum-power-milliwatt = <2000>;
+		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
+		/* tx-disable-gpios = <&sfp3_csr 0 GPIO_ACTIVE_HIGH>; */
+		los-gpios = <&sfp3_csr 4 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&sfp3_csr 5 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sfp3_csr 7 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &crypto {
@@ -236,6 +258,31 @@ temperature-sensor@4d {
 				vcc-supply = <&sb_3v3>;
 			};
 		};
+
+		i2c@7 {
+			reg = <0x7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2c-mux@75 {
+				compatible = "nxp,pca9547";
+				reg = <0x75>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sfp2_i2c: i2c@4 {
+					reg = <0x4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+
+				sfp3_i2c: i2c@5 {
+					reg = <0x5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
 	};
 };
 
-- 
2.25.1

[PATCH v3 10/10] arm64: dts: ls1046a-qds: describe the two on-board SFP+ cages

[Ioana Ciornei]

Describe the two SFP+ cages present on the LS1046AQDS board and their
associated I2C buses and GPIO lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none
Changes in v3:
- Moved the reg property before address/cells-size.

 .../boot/dts/freescale/fsl-ls1046a-qds.dts    | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index 812cf1c5d7f4..48a6c08fcea8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -42,6 +42,21 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	sfp1: sfp-1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfp1_i2c>;
+		maximum-power-milliwatt = <2000>;
+		mod-def0-gpios = <&stat_pres2 6 GPIO_ACTIVE_LOW>;
+	};
+
+	sfp2: sfp-2 {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfp2_i2c>;
+		maximum-power-milliwatt = <2000>;
+		mod-def0-gpios = <&stat_pres2 7 GPIO_ACTIVE_LOW>;
+	};
+
 };
 
 &dspi {
@@ -139,6 +154,31 @@ temp-sensor@4c {
 				reg = <0x4c>;
 			};
 		};
+
+		i2c@7 {
+			reg = <0x7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2c-mux@76 {
+				compatible = "nxp,pca9547";
+				reg = <0x76>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sfp1_i2c: i2c@6 {
+					reg = <0x6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+
+				sfp2_i2c: i2c@7 {
+					reg = <0x7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
 	};
 };
 
-- 
2.25.1

Re: [PATCH v3 04/10] mfd: simple-mfd-i2c: add compatible string for LX2160ARDB

[Lee Jones]

On Wed, 17 Sep 2025, Ioana Ciornei wrote:

> Extend the list of supported devices with the QIXIS FPGA found on the
> LX2160ARDB board.
> 
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - none
> Changes in v3:
> - none
> 
>  drivers/mfd/simple-mfd-i2c.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c
> index 63ac26388860..6fbe85437d8d 100644
> --- a/drivers/mfd/simple-mfd-i2c.c
> +++ b/drivers/mfd/simple-mfd-i2c.c
> @@ -115,6 +115,7 @@ static const struct of_device_id simple_mfd_i2c_of_match[] = {
>  	{ .compatible = "maxim,max5970", .data = &maxim_max5970},
>  	{ .compatible = "maxim,max5978", .data = &maxim_max5970},
>  	{ .compatible = "maxim,max77705-battery", .data = &maxim_mon_max77705},
> +	{ .compatible = "fsl,lx2160ardb-fpga" },
>  	{ .compatible = "fsl,lx2160aqds-fpga" },
>  	{ .compatible = "fsl,ls1028aqds-fpga" },
>  	{ .compatible = "spacemit,p1", .data = &spacemit_p1, },

Please keep alphabetical.

-- 
Lee Jones [李琼斯]

Re: [PATCH v3 02/10] dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3840 bytes --]

On Wed, Sep 17, 2025 at 12:04:14PM +0300, Ioana Ciornei wrote:
> Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.
> 
> Since the register map exposed by the LX2160ARDB's FPGA also contains
> two GPIO controllers, accept the necessary GPIO pattern property.
> At the same time, add the #address-cells and #size-cells properties as
> valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
> addressable.
> 
> This is necessary because when defining child devices such as the GPIO
> controller described in the added example, the child device needs a the
> reg property to properly identify its register location in the parent
> I2C device address space.
> 
> Impose this restriction for the new compatible through an if-statement.
> 
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Enforce a unit address on the child gpios nodes (remove the ?)
> - Enforce the use of unit addresses by having #address-size and
>   #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
> Changes in v3:
> - Replace the trivial-gpio reference with an explicit mention of the
>   accepted child gpio compatible.
> - Reword the commit message.
> - Add the 'else' case to the if statement.
> 
>  .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 58 +++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> index 28b37772fb65..e889dac052e7 100644
> --- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> +++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> @@ -22,6 +22,13 @@ properties:
>                - fsl,lx2160aqds-fpga
>            - const: fsl,fpga-qixis-i2c
>            - const: simple-mfd
> +      - const: fsl,lx2160ardb-fpga

How come this is not compatible with fsl,fpga-qixis-i2c ? Seems like
that device has a feature subset of that one, given your changes here.

> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0
>  
>    interrupts:
>      maxItems: 1
> @@ -32,10 +39,37 @@ properties:
>    mux-controller:
>      $ref: /schemas/mux/reg-mux.yaml
>  
> +patternProperties:
> +  "^gpio@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: true
> +
> +    properties:
> +      compatible:
> +        contains:
> +          enum:
> +            - fsl,lx2160ardb-fpga-gpio-sfp
> +
>  required:
>    - compatible
>    - reg
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,lx2160ardb-fpga
> +    then:
> +      required:
> +        - "#address-cells"
> +        - "#size-cells"
> +    else:
> +      properties:
> +        "#address-cells": false
> +        "#size-cells": false
> +
>  additionalProperties: false
>  
>  examples:
> @@ -68,3 +102,27 @@ examples:
>          };
>      };
>  
> +  - |
> +    i2c {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        board-control@66 {
> +            compatible = "fsl,lx2160ardb-fpga";
> +            reg = <0x66>;
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            gpio@19 {
> +                compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
> +                reg = <0x19>;
> +                gpio-controller;
> +                #gpio-cells = <2>;
> +                gpio-line-names =
> +                    "SFP2_TX_EN", "",
> +                    "", "",
> +                    "SFP2_RX_LOS", "SFP2_TX_FAULT",
> +                    "", "SFP2_MOD_ABS";
> +            };
> +        };
> +    };
> -- 
> 2.25.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v3 05/10] gpio: regmap: add the .fixed_direction_output configuration parameter

[Bartosz Golaszewski]

On Wed, 17 Sep 2025 11:04:17 +0200, Ioana Ciornei <ioana.ciornei@nxp.com> said:
> There are GPIO controllers such as the one present in the LX2160ARDB
> QIXIS FPGA which have fixed-direction input and output GPIO lines mixed
> together in a single register. This cannot be modeled using the
> gpio-regmap as-is since there is no way to present the true direction of
> a GPIO line.
>
> In order to make this use case possible, add a new configuration
> parameter - fixed_direction_output - into the gpio_regmap_config
> structure. This will enable user drivers to provide a bitmap that
> represents the fixed direction of the GPIO lines.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Add the fixed_direction_output bitmap to the gpio_regmap_config
> Changes in v3:
> - Make a deep copy of the new bitmap.
> - Remove the offset check against the ngpio.
> - Added documentation for the new config field.
>
>  drivers/gpio/gpio-regmap.c  | 18 ++++++++++++++++++
>  include/linux/gpio/regmap.h |  6 ++++++
>  2 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
> index e8a32dfebdcb..9edd79b5c10e 100644
> --- a/drivers/gpio/gpio-regmap.c
> +++ b/drivers/gpio/gpio-regmap.c
> @@ -31,6 +31,7 @@ struct gpio_regmap {
>  	unsigned int reg_clr_base;
>  	unsigned int reg_dir_in_base;
>  	unsigned int reg_dir_out_base;
> +	unsigned long *fixed_direction_output;
>
>  	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
>  			      unsigned int offset, unsigned int *reg,
> @@ -129,6 +130,13 @@ static int gpio_regmap_get_direction(struct gpio_chip *chip,
>  	unsigned int base, val, reg, mask;
>  	int invert, ret;
>
> +	if (gpio->fixed_direction_output) {
> +		if (test_bit(offset, gpio->fixed_direction_output))
> +			return GPIO_LINE_DIRECTION_OUT;
> +		else
> +			return GPIO_LINE_DIRECTION_IN;
> +	}
> +
>  	if (gpio->reg_dat_base && !gpio->reg_set_base)
>  		return GPIO_LINE_DIRECTION_IN;
>  	if (gpio->reg_set_base && !gpio->reg_dat_base)
> @@ -277,6 +285,16 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config
>  			return ERR_PTR(ret);
>  	}
>
> +	if (config->fixed_direction_output) {
> +		gpio->fixed_direction_output = devm_bitmap_alloc(config->parent,
> +								 chip->ngpio,
> +								 GFP_KERNEL);

Please don't use devres hidden in what is effectively a library function for
drivers. You have no guarantee this will always be used in probe or that the
life-time of this will end with the associated device's detach. Just use
a regular bitmap_alloc().

Bart

> +		if (!gpio->fixed_direction_output)
> +			return ERR_PTR(-ENOMEM);
> +		bitmap_copy(gpio->fixed_direction_output,
> +			    config->fixed_direction_output, chip->ngpio);
> +	}
> +
>  	/* if not set, assume there is only one register */
>  	gpio->ngpio_per_reg = config->ngpio_per_reg;
>  	if (!gpio->ngpio_per_reg)
> diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h
> index c722c67668c6..8d3d595bfdd3 100644
> --- a/include/linux/gpio/regmap.h
> +++ b/include/linux/gpio/regmap.h
> @@ -37,6 +37,10 @@ struct regmap;
>   *			offset to a register/bitmask pair. If not
>   *			given the default gpio_regmap_simple_xlate()
>   *			is used.
> + * @fixed_direction_output:
> + *			(Optional) Bitmap representing the fixed direction of
> + *			the GPIO lines. Useful when there are GPIO lines with a
> + *			fixed direction mixed together in the same register.
>   * @drvdata:		(Optional) Pointer to driver specific data which is
>   *			not used by gpio-remap but is provided "as is" to the
>   *			driver callback(s).
> @@ -78,6 +82,8 @@ struct gpio_regmap_config {
>  	int ngpio_per_reg;
>  	struct irq_domain *irq_domain;
>
> +	unsigned long *fixed_direction_output;
> +
>  	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
>  			      unsigned int offset, unsigned int *reg,
>  			      unsigned int *mask);
> --
> 2.25.1
>
>

Re: [PATCH v3 04/10] mfd: simple-mfd-i2c: add compatible string for LX2160ARDB

[Ioana Ciornei]

On Wed, Sep 17, 2025 at 10:20:06AM +0100, Lee Jones wrote:
> On Wed, 17 Sep 2025, Ioana Ciornei wrote:
> 
> > Extend the list of supported devices with the QIXIS FPGA found on the
> > LX2160ARDB board.
> > 
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - none
> > Changes in v3:
> > - none
> > 
> >  drivers/mfd/simple-mfd-i2c.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c
> > index 63ac26388860..6fbe85437d8d 100644
> > --- a/drivers/mfd/simple-mfd-i2c.c
> > +++ b/drivers/mfd/simple-mfd-i2c.c
> > @@ -115,6 +115,7 @@ static const struct of_device_id simple_mfd_i2c_of_match[] = {
> >  	{ .compatible = "maxim,max5970", .data = &maxim_max5970},
> >  	{ .compatible = "maxim,max5978", .data = &maxim_max5970},
> >  	{ .compatible = "maxim,max77705-battery", .data = &maxim_mon_max77705},
> > +	{ .compatible = "fsl,lx2160ardb-fpga" },
> >  	{ .compatible = "fsl,lx2160aqds-fpga" },
> >  	{ .compatible = "fsl,ls1028aqds-fpga" },
> >  	{ .compatible = "spacemit,p1", .data = &spacemit_p1, },
> 
> Please keep alphabetical.

Ok, sure.

Even without this patch, the fsl compatible strings are not in
alphabetical order. Are you ok with adding another patch that fixes the
initial issue or do you want me to just do the changes in a single
patch?

Ioana

Re: [PATCH v3 04/10] mfd: simple-mfd-i2c: add compatible string for LX2160ARDB

[Ioana Ciornei]

On Thu, Sep 18, 2025 at 02:15:13PM +0300, Ioana Ciornei wrote:
> On Wed, Sep 17, 2025 at 10:20:06AM +0100, Lee Jones wrote:
> > On Wed, 17 Sep 2025, Ioana Ciornei wrote:
> > 
> > > Extend the list of supported devices with the QIXIS FPGA found on the
> > > LX2160ARDB board.
> > > 
> > > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > > ---
> > > Changes in v2:
> > > - none
> > > Changes in v3:
> > > - none
> > > 
> > >  drivers/mfd/simple-mfd-i2c.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c
> > > index 63ac26388860..6fbe85437d8d 100644
> > > --- a/drivers/mfd/simple-mfd-i2c.c
> > > +++ b/drivers/mfd/simple-mfd-i2c.c
> > > @@ -115,6 +115,7 @@ static const struct of_device_id simple_mfd_i2c_of_match[] = {
> > >  	{ .compatible = "maxim,max5970", .data = &maxim_max5970},
> > >  	{ .compatible = "maxim,max5978", .data = &maxim_max5970},
> > >  	{ .compatible = "maxim,max77705-battery", .data = &maxim_mon_max77705},
> > > +	{ .compatible = "fsl,lx2160ardb-fpga" },
> > >  	{ .compatible = "fsl,lx2160aqds-fpga" },
> > >  	{ .compatible = "fsl,ls1028aqds-fpga" },
> > >  	{ .compatible = "spacemit,p1", .data = &spacemit_p1, },
> > 
> > Please keep alphabetical.
> 
> Ok, sure.
> 
> Even without this patch, the fsl compatible strings are not in
> alphabetical order. Are you ok with adding another patch that fixes the
> initial issue or do you want me to just do the changes in a single
> patch?
> 

I just realized that they are not in alphabetical order even when
looking at the other compatible strings other than the fsl ones. I will
add another patch to fix all of them since.

Re: [PATCH v3 02/10] dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA

[Ioana Ciornei]

On Wed, Sep 17, 2025 at 08:19:42PM +0100, Conor Dooley wrote:
> On Wed, Sep 17, 2025 at 12:04:14PM +0300, Ioana Ciornei wrote:
> > Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.
> > 
> > Since the register map exposed by the LX2160ARDB's FPGA also contains
> > two GPIO controllers, accept the necessary GPIO pattern property.
> > At the same time, add the #address-cells and #size-cells properties as
> > valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
> > addressable.
> > 
> > This is necessary because when defining child devices such as the GPIO
> > controller described in the added example, the child device needs a the
> > reg property to properly identify its register location in the parent
> > I2C device address space.
> > 
> > Impose this restriction for the new compatible through an if-statement.
> > 
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - Enforce a unit address on the child gpios nodes (remove the ?)
> > - Enforce the use of unit addresses by having #address-size and
> >   #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
> > Changes in v3:
> > - Replace the trivial-gpio reference with an explicit mention of the
> >   accepted child gpio compatible.
> > - Reword the commit message.
> > - Add the 'else' case to the if statement.
> > 
> >  .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 58 +++++++++++++++++++
> >  1 file changed, 58 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> > index 28b37772fb65..e889dac052e7 100644
> > --- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> > +++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> > @@ -22,6 +22,13 @@ properties:
> >                - fsl,lx2160aqds-fpga
> >            - const: fsl,fpga-qixis-i2c
> >            - const: simple-mfd
> > +      - const: fsl,lx2160ardb-fpga
> 
> How come this is not compatible with fsl,fpga-qixis-i2c ? Seems like
> that device has a feature subset of that one, given your changes here.

The feature set exposed by the devices is highly dependent on the board
type, meaning that even though the FPGA found on the LX2160AQDS board
(fsl,lx2160aqds-fpga) works in the same way in terms of access over I2C
as the one found on the LX2160ARDB (fsl,lx2160ardb-fpga added here), the
register map inside the device space its different since there are
different on-board devices to be controlled.

I didn't add the fsl,fpga-qixis-i2c as a fallback because there is no
driver probing it and it seemed to not make sense / be necessary.

Ioana

Re: [PATCH v3 02/10] dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2908 bytes --]

On Thu, Sep 18, 2025 at 02:44:06PM +0300, Ioana Ciornei wrote:
> On Wed, Sep 17, 2025 at 08:19:42PM +0100, Conor Dooley wrote:
> > On Wed, Sep 17, 2025 at 12:04:14PM +0300, Ioana Ciornei wrote:
> > > Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.
> > > 
> > > Since the register map exposed by the LX2160ARDB's FPGA also contains
> > > two GPIO controllers, accept the necessary GPIO pattern property.
> > > At the same time, add the #address-cells and #size-cells properties as
> > > valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
> > > addressable.
> > > 
> > > This is necessary because when defining child devices such as the GPIO
> > > controller described in the added example, the child device needs a the
> > > reg property to properly identify its register location in the parent
> > > I2C device address space.
> > > 
> > > Impose this restriction for the new compatible through an if-statement.
> > > 
> > > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > > ---
> > > Changes in v2:
> > > - Enforce a unit address on the child gpios nodes (remove the ?)
> > > - Enforce the use of unit addresses by having #address-size and
> > >   #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
> > > Changes in v3:
> > > - Replace the trivial-gpio reference with an explicit mention of the
> > >   accepted child gpio compatible.
> > > - Reword the commit message.
> > > - Add the 'else' case to the if statement.
> > > 
> > >  .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 58 +++++++++++++++++++
> > >  1 file changed, 58 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> > > index 28b37772fb65..e889dac052e7 100644
> > > --- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> > > +++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> > > @@ -22,6 +22,13 @@ properties:
> > >                - fsl,lx2160aqds-fpga
> > >            - const: fsl,fpga-qixis-i2c
> > >            - const: simple-mfd
> > > +      - const: fsl,lx2160ardb-fpga
> > 
> > How come this is not compatible with fsl,fpga-qixis-i2c ? Seems like
> > that device has a feature subset of that one, given your changes here.
> 
> The feature set exposed by the devices is highly dependent on the board
> type, meaning that even though the FPGA found on the LX2160AQDS board
> (fsl,lx2160aqds-fpga) works in the same way in terms of access over I2C
> as the one found on the LX2160ARDB (fsl,lx2160ardb-fpga added here), the
> register map inside the device space its different since there are
> different on-board devices to be controlled.

Okay, please cover that in your commit message. With that,
Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH v3 06/10] gpio: add QIXIS FPGA GPIO controller

[Frank Li]

On Wed, Sep 17, 2025 at 12:04:18PM +0300, Ioana Ciornei wrote:
> Add support for the GPIO controller found on some QIXIS FPGAs in
> Layerscape boards such as LX2160ARDB and LS1046AQDS. This driver is
> using gpio-regmap.
>
> A GPIO controller has a maximum of 8 lines (all found in the same
> register). Even within the same controller, the GPIO lines' direction is
> fixed, which mean that both input and output lines are found in the same
> register. This is why the driver also passed to gpio-regmap the newly
> added .fixed_direction_output bitmap to represent the true direction of
> the lines.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
> Changes in v2:
> - Use the newly added .fixed_direction_output bitmap representing
>   the fixed direction of the GPIO lines.
> Changes in v3:
> - Remove 'drivers' from the commit title.
> - Remove the qixis_cpld_gpio_type enum since its not needed.
> - Remove the NULL check for device_get_match_data().
> - Use a bitmap declared on the stack as the config field passed to
>   gpio-regmap.
>
>  drivers/gpio/Kconfig           |   9 +++
>  drivers/gpio/Makefile          |   1 +
>  drivers/gpio/gpio-qixis-fpga.c | 107 +++++++++++++++++++++++++++++++++
>  3 files changed, 117 insertions(+)
>  create mode 100644 drivers/gpio/gpio-qixis-fpga.c
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 81fe3b085f7b..e963a7ee4ce1 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -1962,6 +1962,15 @@ config GPIO_LATCH
>  	  Say yes here to enable a driver for GPIO multiplexers based on latches
>  	  connected to other GPIOs.
>
> +config GPIO_QIXIS_FPGA
> +	tristate "NXP QIXIS FPGA GPIO support"
> +	depends on MFD_SIMPLE_MFD_I2C || COMPILE_TEST
> +	select GPIO_REGMAP
> +	help
> +	  This enables support for the GPIOs found in the QIXIS FPGA which is
> +	  integrated on some NXP Layerscape boards such as LX2160ARDB and
> +	  LS1046AQDS.
> +
>  config GPIO_MOCKUP
>  	tristate "GPIO Testing Driver (DEPRECATED)"
>  	select IRQ_SIM
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index b1593ce92ebe..850c0e086c82 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -144,6 +144,7 @@ obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.o
>  obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
>  obj-$(CONFIG_GPIO_POLARFIRE_SOC)	+= gpio-mpfs.o
>  obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
> +obj-$(CONFIG_GPIO_QIXIS_FPGA)		+= gpio-qixis-fpga.o
>  obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
>  obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
>  obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
> diff --git a/drivers/gpio/gpio-qixis-fpga.c b/drivers/gpio/gpio-qixis-fpga.c
> new file mode 100644
> index 000000000000..048a2cac4f0f
> --- /dev/null
> +++ b/drivers/gpio/gpio-qixis-fpga.c
> @@ -0,0 +1,107 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Layerscape GPIO QIXIS FPGA driver
> + *
> + * Copyright 2025 NXP
> + */
> +
> +#include <linux/device.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/gpio/regmap.h>
> +#include <linux/kernel.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +struct qixis_cpld_gpio_config {
> +	u64 output_lines;
> +};
> +
> +static const struct qixis_cpld_gpio_config lx2160ardb_sfp_cfg = {
> +	.output_lines = BIT(0),
> +};
> +
> +static const struct qixis_cpld_gpio_config ls1046aqds_stat_pres2_cfg = {
> +	.output_lines = 0x0,
> +};
> +
> +static const struct regmap_config regmap_config_8r_8v = {
> +	.reg_bits = 8,
> +	.val_bits = 8,
> +};
> +
> +static int qixis_cpld_gpio_probe(struct platform_device *pdev)
> +{
> +	DECLARE_BITMAP(fixed_direction_output, 8);
> +	const struct qixis_cpld_gpio_config *cfg;
> +	struct gpio_regmap_config config = {0};
> +	struct regmap *regmap;
> +	void __iomem *reg;
> +	u32 base;
> +	int ret;
> +
> +	if (!pdev->dev.parent)
> +		return -ENODEV;
> +
> +	cfg = device_get_match_data(&pdev->dev);
> +
> +	ret = device_property_read_u32(&pdev->dev, "reg", &base);
> +	if (ret)
> +		return ret;
> +
> +	regmap = dev_get_regmap(pdev->dev.parent, NULL);
> +	if (!regmap) {
> +		/* In case there is no regmap configured by the parent device,
> +		 * create our own from the MMIO space.
> +		 */
> +		reg = devm_platform_ioremap_resource(pdev, 0);
> +		if (!reg)
> +			return -ENODEV;
> +
> +		regmap = devm_regmap_init_mmio(&pdev->dev, reg, &regmap_config_8r_8v);
> +		if (!regmap)
> +			return -ENODEV;
> +
> +		/* In this case, the offset of our register is 0 inside the
> +		 * regmap area that we just created.
> +		 */
> +		base = 0;
> +	}
> +	config.reg_dat_base = GPIO_REGMAP_ADDR(base);
> +	config.reg_set_base = GPIO_REGMAP_ADDR(base);
> +
> +	config.drvdata = (void *)cfg;
> +	config.regmap = regmap;
> +	config.parent = &pdev->dev;
> +	config.ngpio_per_reg = 8;
> +	config.ngpio = 8;
> +
> +	bitmap_from_u64(fixed_direction_output, cfg->output_lines);
> +	config.fixed_direction_output = fixed_direction_output;
> +
> +	return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config));
> +}
> +
> +static const struct of_device_id qixis_cpld_gpio_of_match[] = {
> +	{
> +		.compatible = "fsl,lx2160ardb-fpga-gpio-sfp",
> +		.data = &lx2160ardb_sfp_cfg,
> +	},
> +	{
> +		.compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2",
> +		.data = &ls1046aqds_stat_pres2_cfg,
> +	},
> +
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, qixis_cpld_gpio_of_match);
> +
> +static struct platform_driver qixis_cpld_gpio_driver = {
> +	.probe = qixis_cpld_gpio_probe,
> +	.driver = {
> +		.name = "gpio-qixis-cpld",
> +		.of_match_table = qixis_cpld_gpio_of_match,
> +	},
> +};
> +module_platform_driver(qixis_cpld_gpio_driver);
> --
> 2.25.1
>

Re: [PATCH v3 09/10] arm64: dts: lx2160a-rdb: fully describe the two SFP+ cages

[Frank Li]

On Wed, Sep 17, 2025 at 12:04:21PM +0300, Ioana Ciornei wrote:
> Describe the two SFP+ cages found on the LX2160ARDB board with their
> respective I2C buses and GPIO lines.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
> Changes in v2:
> - none
> Changes in v3:
> - Moved the reg property before address/cells-size.
>
>  .../boot/dts/freescale/fsl-lx2160a-rdb.dts    | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> index 4ede1295f29d..1c1ed0c5f016 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -31,6 +31,28 @@ sb_3v3: regulator-sb3v3 {
>  		regulator-boot-on;
>  		regulator-always-on;
>  	};
> +
> +	sfp2: sfp-2 {
> +		compatible = "sff,sfp";
> +		i2c-bus = <&sfp2_i2c>;
> +		maximum-power-milliwatt = <2000>;
> +		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
> +		/* tx-disable-gpios = <&sfp2_csr 0 GPIO_ACTIVE_HIGH>; */
> +		los-gpios = <&sfp2_csr 4 GPIO_ACTIVE_HIGH>;
> +		tx-fault-gpios = <&sfp2_csr 5 GPIO_ACTIVE_HIGH>;
> +		mod-def0-gpios = <&sfp2_csr 7 GPIO_ACTIVE_LOW>;
> +	};
> +
> +	sfp3: sfp-3 {
> +		compatible = "sff,sfp";
> +		i2c-bus = <&sfp3_i2c>;
> +		maximum-power-milliwatt = <2000>;
> +		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
> +		/* tx-disable-gpios = <&sfp3_csr 0 GPIO_ACTIVE_HIGH>; */
> +		los-gpios = <&sfp3_csr 4 GPIO_ACTIVE_HIGH>;
> +		tx-fault-gpios = <&sfp3_csr 5 GPIO_ACTIVE_HIGH>;
> +		mod-def0-gpios = <&sfp3_csr 7 GPIO_ACTIVE_LOW>;
> +	};
>  };
>
>  &crypto {
> @@ -236,6 +258,31 @@ temperature-sensor@4d {
>  				vcc-supply = <&sb_3v3>;
>  			};
>  		};
> +
> +		i2c@7 {
> +			reg = <0x7>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			i2c-mux@75 {
> +				compatible = "nxp,pca9547";
> +				reg = <0x75>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				sfp2_i2c: i2c@4 {
> +					reg = <0x4>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +
> +				sfp3_i2c: i2c@5 {
> +					reg = <0x5>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +				};
> +			};
> +		};
>  	};
>  };
>
> --
> 2.25.1
>

Re: [PATCH v3 05/10] gpio: regmap: add the .fixed_direction_output configuration parameter

[Ioana Ciornei]

On Thu, Sep 18, 2025 at 03:55:16AM -0700, Bartosz Golaszewski wrote:
> On Wed, 17 Sep 2025 11:04:17 +0200, Ioana Ciornei <ioana.ciornei@nxp.com> said:
> > There are GPIO controllers such as the one present in the LX2160ARDB
> > QIXIS FPGA which have fixed-direction input and output GPIO lines mixed
> > together in a single register. This cannot be modeled using the
> > gpio-regmap as-is since there is no way to present the true direction of
> > a GPIO line.
> >
> > In order to make this use case possible, add a new configuration
> > parameter - fixed_direction_output - into the gpio_regmap_config
> > structure. This will enable user drivers to provide a bitmap that
> > represents the fixed direction of the GPIO lines.
> >
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - Add the fixed_direction_output bitmap to the gpio_regmap_config
> > Changes in v3:
> > - Make a deep copy of the new bitmap.
> > - Remove the offset check against the ngpio.
> > - Added documentation for the new config field.
> >
> >  drivers/gpio/gpio-regmap.c  | 18 ++++++++++++++++++
> >  include/linux/gpio/regmap.h |  6 ++++++
> >  2 files changed, 24 insertions(+)
> >
> > diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
> > index e8a32dfebdcb..9edd79b5c10e 100644
> > --- a/drivers/gpio/gpio-regmap.c
> > +++ b/drivers/gpio/gpio-regmap.c
> > @@ -31,6 +31,7 @@ struct gpio_regmap {
> >  	unsigned int reg_clr_base;
> >  	unsigned int reg_dir_in_base;
> >  	unsigned int reg_dir_out_base;
> > +	unsigned long *fixed_direction_output;
> >
> >  	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
> >  			      unsigned int offset, unsigned int *reg,
> > @@ -129,6 +130,13 @@ static int gpio_regmap_get_direction(struct gpio_chip *chip,
> >  	unsigned int base, val, reg, mask;
> >  	int invert, ret;
> >
> > +	if (gpio->fixed_direction_output) {
> > +		if (test_bit(offset, gpio->fixed_direction_output))
> > +			return GPIO_LINE_DIRECTION_OUT;
> > +		else
> > +			return GPIO_LINE_DIRECTION_IN;
> > +	}
> > +
> >  	if (gpio->reg_dat_base && !gpio->reg_set_base)
> >  		return GPIO_LINE_DIRECTION_IN;
> >  	if (gpio->reg_set_base && !gpio->reg_dat_base)
> > @@ -277,6 +285,16 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config
> >  			return ERR_PTR(ret);
> >  	}
> >
> > +	if (config->fixed_direction_output) {
> > +		gpio->fixed_direction_output = devm_bitmap_alloc(config->parent,
> > +								 chip->ngpio,
> > +								 GFP_KERNEL);
> 
> Please don't use devres hidden in what is effectively a library function for
> drivers. You have no guarantee this will always be used in probe or that the
> life-time of this will end with the associated device's detach. Just use
> a regular bitmap_alloc().

Ok, sure. I will switch to bitmap_alloc() and bitmap_free().

Ioana