[PATCH v3 6/8] dt-bindings: soc: renesas: Add the Renesas RZ/N1 GPIO Interrupt Multiplexer

Herve Codina (Schneider Electric)
2025-09-18T10:40:42Z

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
.../soc/renesas/renesas,rzn1-gpioirqmux.yaml | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml
new file mode 100644
index 000000000000..21c6b6e1fa9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer
+
+description: |
+ The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt
+ lines to the interrupt controller available in the SoC.
+
+ It selects up to 8 of the 96 GPIO interrupt lines available and connect them
+ to 8 output interrupt lines.
+
+maintainers:
+ - Herve Codina <herve.codina@bootlin.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a06g032-gpioirqmux
+ - const: renesas,rzn1-gpioirqmux
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 0
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-map-mask:
+ items:
+ - const: 0x7f
+
+ interrupt-map:
+ description:
+ Specifies the mapping from external GPIO interrupt lines to the output
+ interrupts. The array items have to be ordered with the first item
+ related to the output line 0 (IRQ 103), the next one to the output line 1
+ (IRQ 104) and so on up to the output line 8 (IRQ 110).
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#interrupt-cells"
+ - interrupt-map-mask
+ - interrupt-map
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gic: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ };
+
+ interrupt-controller@51000480 {
+ compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
+ reg = <0x51000480 0x20>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x7f>;
+ /*
+ * The child interrupt number is computed using the following formula:
+ * gpio_bank * 32 + gpio_number
+ *
+ * with:
+ * - gpio_bank: The GPIO bank number
+ * - 0 for GPIO0A,
+ * - 1 for GPIO1A,
+ * - 2 for GPIO2A
+ * - gpio_number: Number of the gpio in the bank (0..31)
+ */
+ interrupt-map =
+ <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1A.0 */
+ <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* GPIO2A.25 */
+ <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* GPIO0A.9 */
+ };
--
2.51.0