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From: Xu Lu <luxu.kernel@bytedance.com>
To: corbet@lwn.net, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, paul.walmsley@sifive.com,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
	will@kernel.org, peterz@infradead.org, boqun.feng@gmail.com,
	mark.rutland@arm.com, parri.andrea@gmail.com,
	ajones@ventanamicro.com, brs@rivosinc.com, anup@brainfault.org,
	atish.patra@linux.dev, pbonzini@redhat.com, shuah@kernel.org
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com,
	linux-doc@vger.kernel.org, kvm@vger.kernel.org,
	kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
	Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH v3 1/8] riscv: add ISA extension parsing for Zalasr
Date: Fri, 19 Sep 2025 15:37:07 +0800	[thread overview]
Message-ID: <20250919073714.83063-2-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20250919073714.83063-1-luxu.kernel@bytedance.com>

Add parsing for Zalasr ISA extension.

Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index affd63e11b0a3..ae3852c4f2ca2 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -106,6 +106,7 @@
 #define RISCV_ISA_EXT_ZAAMO		97
 #define RISCV_ISA_EXT_ZALRSC		98
 #define RISCV_ISA_EXT_ZICBOP		99
+#define RISCV_ISA_EXT_ZALASR		100
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 743d53415572e..bf9d3d92bf372 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -472,6 +472,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
 	__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
 	__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
+	__RISCV_ISA_EXT_DATA(zalasr, RISCV_ISA_EXT_ZALASR),
 	__RISCV_ISA_EXT_DATA(zalrsc, RISCV_ISA_EXT_ZALRSC),
 	__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
 	__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
-- 
2.20.1


  reply	other threads:[~2025-09-19  7:37 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-19  7:37 [PATCH v3 0/8] riscv: Add Zalasr ISA extension support Xu Lu
2025-09-19  7:37 ` Xu Lu [this message]
2025-09-19  7:37 ` [PATCH v3 2/8] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
2025-09-19  7:37 ` [PATCH v3 3/8] riscv: hwprobe: Export Zalasr extension Xu Lu
2025-09-19  7:37 ` [PATCH v3 4/8] riscv: Introduce Zalasr instructions Xu Lu
2025-09-19  7:37 ` [PATCH v3 5/8] riscv: Use Zalasr for smp_load_acquire/smp_store_release Xu Lu
2025-09-19  7:37 ` [PATCH v3 6/8] riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations Xu Lu
2025-09-20 14:52   ` kernel test robot
2025-09-19  7:37 ` [PATCH v3 7/8] RISC-V: KVM: Allow Zalasr extensions for Guest/VM Xu Lu
2025-09-19  7:37 ` [PATCH v3 8/8] KVM: riscv: selftests: Add Zalasr extensions to get-reg-list test Xu Lu
2025-09-19 10:04 ` [PATCH v3 0/8] riscv: Add Zalasr ISA extension support Andrea Parri
2025-09-19 10:39   ` [External] " Xu Lu
2025-09-19 10:53     ` Xu Lu
2025-09-19 11:06       ` Andrea Parri
2025-09-19 12:12         ` Xu Lu

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