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Fri, 19 Sep 2025 02:36:29 -0700 From: Kartik Rajput To: , , , , , , , , , , CC: Prathamesh Shete , Kartik Rajput Subject: [PATCH 1/2] dt-bindings: gpio: Add Tegra410 support Date: Fri, 19 Sep 2025 15:06:26 +0530 Message-ID: <20250919093627.605059-1-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4B:EE_|CH1PPF946CC24FA:EE_ X-MS-Office365-Filtering-Correlation-Id: 76458936-d395-464d-f897-08ddf7601030 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026|7416014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?umw34cdvapC2DsIKyrBf1rGahFpQa+Y7RBoxsifQQ99R+yD5EZQA9OfkxSRB?= =?us-ascii?Q?MzLRV6g3Hcbq6SF6TKOmaUD/N6eiNbZBR5G8ynkWUdvwoLtcwixv/cm1EN/F?= =?us-ascii?Q?qGVqjdsiPTIeUPLnxWPN8PhdFCMNRKy573ghEuwSz7x5yRXEH4aTUOms54R6?= =?us-ascii?Q?2CVb4lvaR24XPFXYnQrc+BqqE57QjnPXTcVnML6EEFrVAFd7h2H7CdAhpMH4?= =?us-ascii?Q?vc514lrd/4XIzsV+QuFuAYk6kCUGnCedJFTQN481eXDMQNBuuMzqbnvdzt3G?= =?us-ascii?Q?P4nIVjmKtXKnxLWY3ki7e+YTai2rFGnkb2zkGmtmYhE8w9Upgcg+le0hLYzm?= =?us-ascii?Q?cH0qvDFt3BM8p+Okoub7KYRxvbu9qNv/yNRVPGfGlajrSq6uXB5bFgYITeCh?= =?us-ascii?Q?GC8lfcNU/ddPvbIikiLWipDr6WYbgLOmY+lET74u0mmBd8NPOqAo3MVoFxBV?= =?us-ascii?Q?TasAb3zMgcoH307dmkWxpg0uC29f91RNWRGzrC99xw4poFGc43NB4pWo+ao9?= =?us-ascii?Q?i7DG8/+vl2b+1txZTP0DHi/siGRyn/2chb4sYZdrtq0eoAT3cYVeR0W/ZSPU?= =?us-ascii?Q?Ib7jYiKBaiLynZmSg9F5kW8GgPuSvx9ziXWvVNcjJ2cRigvDA7lsWQt3lv/4?= =?us-ascii?Q?hpidgmQmdbwfM0LmOLCtjUZHsFEjEVNMgOo6M69Ed1pGS2c1Y2nliY3gmuAG?= =?us-ascii?Q?oXIuUc+7o6fTF/m4TXLkferYd5HZOPFXCjVkOlqByj9nm1NlWRQzQoSg/X40?= =?us-ascii?Q?EPGRyBdvtLP/+xvksor/KhWEaJ2DGhSVA91umfgSTHKVbXJLeMU2riZ8f15p?= =?us-ascii?Q?/Nkso0j1JoGYkFzjAv+8XrUa1chSmg0MLqEQlD/DhmVbAwYiGAPFGwRZe3Uo?= =?us-ascii?Q?NzMHFhnrKEyXlmYCEMNGjbnFhhBzclkAa6qNqI2ulMnCj0cPbM2wy12ykTcQ?= =?us-ascii?Q?3V1Tt32nqVb0a0cNfcDlsYcpvz66H3BSIKYLK+fgGz79jDoIkuiRlIsZtPoQ?= =?us-ascii?Q?t5B2t2PvpkGWhJI4HHkmnMfBIbtC8RVnGYTgVR+N+qJwfuFrKgEEl5etZcWM?= =?us-ascii?Q?ijCBH42H98JPiPb2a9KedrF2pjr0sKMX8AQhxKl8dw5gbperuP0CCEEU0ML8?= =?us-ascii?Q?Hv1EWX2UKLZBLkMqJxOVvd1F7+k/YAYg+V212RyelC/alNWe/Si/a+FOQ+/q?= =?us-ascii?Q?0xf1ow6PeYemYdGWcb6S7UHnMcZe/3FtpSUY89gDIm4q0JGxRgwz0w/8Vk2e?= =?us-ascii?Q?i9GTd5pb39pGbAeoLeoM5JFXedQRdkJfUl7OEfinYoiEs6Fpcg7A00gvkuwi?= =?us-ascii?Q?WBm9ITyA+0wueuMngAg/3/6OM1t9d62RlMD+ZWn8lq8fXv9h7A4wwGErB3Fa?= =?us-ascii?Q?+LGrDDs5axt0wOh4lx26S6PnrcFBBmegqhKoou7OxLQ/b7QyBZi8DwhD1RaI?= =?us-ascii?Q?W7koFVzF+x7+Bp34pgb3tbjJuCfh6pPTm3JlfZhwZ4OJwlqGSe0UXv7KHmfE?= =?us-ascii?Q?EFvcmRSSvLXo8Ab+Jz+N7vjqIGQIKnuBGwey4EnyvVg1lphHHr8HKU65dA?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2025 09:36:51.5062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76458936-d395-464d-f897-08ddf7601030 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF946CC24FA From: Prathamesh Shete Add the port definitions for the main GPIO controller found on Tegra410. Signed-off-by: Prathamesh Shete Signed-off-by: Kartik Rajput --- include/dt-bindings/gpio/tegra410-gpio.h | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 include/dt-bindings/gpio/tegra410-gpio.h diff --git a/include/dt-bindings/gpio/tegra410-gpio.h b/include/dt-bindings/gpio/tegra410-gpio.h new file mode 100644 index 000000000000..e4d042fbacb2 --- /dev/null +++ b/include/dt-bindings/gpio/tegra410-gpio.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ + +/* + * This header provides constants for the nvidia,tegra410-gpio DT binding. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA410_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA410_GPIO_H + +#include + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA410_MAIN_GPIO_PORT_A 0 +#define TEGRA410_MAIN_GPIO_PORT_B 1 +#define TEGRA410_MAIN_GPIO_PORT_C 2 +#define TEGRA410_MAIN_GPIO_PORT_D 3 +#define TEGRA410_MAIN_GPIO_PORT_E 4 +#define TEGRA410_MAIN_GPIO_PORT_I 5 +#define TEGRA410_MAIN_GPIO_PORT_J 6 +#define TEGRA410_MAIN_GPIO_PORT_K 7 +#define TEGRA410_MAIN_GPIO_PORT_L 8 +#define TEGRA410_MAIN_GPIO_PORT_M 9 +#define TEGRA410_MAIN_GPIO_PORT_N 10 +#define TEGRA410_MAIN_GPIO_PORT_P 11 +#define TEGRA410_MAIN_GPIO_PORT_Q 12 +#define TEGRA410_MAIN_GPIO_PORT_R 13 + +#define TEGRA410_MAIN_GPIO(port, offset) \ + ((TEGRA410_MAIN_GPIO_PORT_##port * 8) + (offset)) + +#endif -- 2.43.0