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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2025 12:39:08.9192 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 715e5d6f-7644-43a7-d0b2-08ddf7798750 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4234 From: Sai Krishna Potthuri Some vendors will define their own interrupts, current interrupt service routine handles only interrupts defined by the JEDEC standard. Add provision to handle vendor specific interrupts by defining vendor specific vops. Signed-off-by: Sai Krishna Potthuri Signed-off-by: Ajay Neeli --- drivers/ufs/core/ufshcd-priv.h | 8 ++++++++ drivers/ufs/core/ufshcd.c | 3 +++ include/ufs/ufshcd.h | 2 ++ include/ufs/ufshci.h | 3 +++ 4 files changed, 16 insertions(+) diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index d0a2c96..04a31f0 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -118,6 +118,14 @@ static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba) return ufshcd_readl(hba, REG_UFS_VERSION); } +static inline irqreturn_t ufshcd_vops_isr(struct ufs_hba *hba, u32 intr_status) +{ + if (hba->vops && hba->vops->isr) + return hba->vops->isr(hba, intr_status); + + return 0; +} + static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba, bool up, unsigned long target_freq, enum ufs_notify_change_status status) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 5442bb8..7a6dde8 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -7069,6 +7069,9 @@ static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) if (intr_status & MCQ_CQ_EVENT_STATUS) retval |= ufshcd_handle_mcq_cq_events(hba); + if (intr_status & UFSHCD_VENDOR_IS_MASK) + retval |= ufshcd_vops_isr(hba, intr_status); + return retval; } diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 1d39437..64c958e 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -337,6 +337,7 @@ struct ufs_pwr_mode_info { * @config_esi: called to config Event Specific Interrupt * @config_scsi_dev: called to configure SCSI device parameters * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed + * @isr: called to handle vendor specific interrupts */ struct ufs_hba_variant_ops { const char *name; @@ -386,6 +387,7 @@ struct ufs_hba_variant_ops { int (*config_esi)(struct ufs_hba *hba); void (*config_scsi_dev)(struct scsi_device *sdev); u32 (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq); + irqreturn_t (*isr)(struct ufs_hba *hba, u32 intr_status); }; /* clock gating state */ diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h index 612500a..2844772 100644 --- a/include/ufs/ufshci.h +++ b/include/ufs/ufshci.h @@ -185,6 +185,9 @@ static inline u32 ufshci_version(u32 major, u32 minor) #define CRYPTO_ENGINE_FATAL_ERROR 0x40000 #define MCQ_CQ_EVENT_STATUS 0x100000 +/* Other than above mentioned bits are treated as Vendor specific status bits */ +#define UFSHCD_VENDOR_IS_MASK 0xFFE8F000 + #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ UIC_HIBERNATE_EXIT) -- 1.8.3.1