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([2a01:e0a:f:6020:9dd0:62bf:d369:14ce]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3ee07407fa3sm8367224f8f.21.2025.09.19.08.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Sep 2025 08:58:22 -0700 (PDT) From: Vincent Guittot To: chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com, s32@nxp.com, bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Ionut.Vicovan@nxp.com, larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com, ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com, Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev Cc: cassel@kernel.org Subject: [PATCH 0/4 v2] PCI: s32g: Add support for PCIe controller Date: Fri, 19 Sep 2025 17:58:18 +0200 Message-ID: <20250919155821.95334-1-vincent.guittot@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The S32G SoC family has 2 PCIe controllers based on Designware IP. Add the support for Host mode. Change since v1: - Cleanup DT binding - Removed useless description and fixed typo, naming and indentation. - Removed nxp,phy-mode binding until we agreed on a generic binding. Default (crnss) mode is used for now. Generic binding wil be discussed in a separate patch. - Removed max-link-speed and num-lanes which are coming from snps,dw-pcie-common.yaml. They are needed only if to restrict from the the default hw config. - Added unevaluatedProperties: false - Keep Phys in host node until dw support Root Port node. - Removed nxp-s32g-pcie-phy-submode.h until there is a generic clock and spectrum binding. - Rename files to start with pcie-s32g instead of pci-s32g - Cleanup pcie-s32-reg.h and use dw_pcie_find_capability() - cleanup and rename in s32g-pcie.c in addtion to remove useless check or duplicate code. - dw_pcie_suspend/resume_noirq() doesn't woork, need to set child device to reach lowest state. - Added L: imx@lists.linux.dev in MAINTAINERS Vincent Guittot (3): dt-bindings: PCI: s32g: Add NXP PCIe controller PCI: s32g: Add initial PCIe support (RC) MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver .../devicetree/bindings/pci/nxp,s32-pcie.yaml | 131 ++++ MAINTAINERS | 4 + drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-s32g-regs.h | 61 ++ drivers/pci/controller/dwc/pcie-s32g.c | 578 ++++++++++++++++++ 7 files changed, 787 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-s32g-regs.h create mode 100644 drivers/pci/controller/dwc/pcie-s32g.c -- 2.43.0