From: Junhui Liu <junhui.liu@pigmoral.tech>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Junhui Liu <junhui.liu@pigmoral.tech>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@sifive.com>,
Conor Dooley <conor@kernel.org>,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org
Subject: [PATCH v2 07/11] riscv: Add Anlogic SoC famly Kconfig support
Date: Mon, 22 Sep 2025 20:46:37 +0800 [thread overview]
Message-ID: <20250922-dr1v90-basic-dt-v2-7-64d28500cb37@pigmoral.tech> (raw)
In-Reply-To: <20250922-dr1v90-basic-dt-v2-0-64d28500cb37@pigmoral.tech>
The first SoC in the Anlogic series is DR1V90, which contains a RISC-V
core from Nuclei.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 61ceae0aa27a6fa3a91da6a46becfd96da99fd09..c1c0681f4364647477c50518725d9323922ff270 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -7,6 +7,11 @@ config ARCH_ANDES
help
This enables support for Andes SoC platform hardware.
+config ARCH_ANLOGIC
+ bool "Anlogic SoCs"
+ help
+ This enables support for Anlogic SoC platform hardware.
+
config ARCH_MICROCHIP_POLARFIRE
def_bool ARCH_MICROCHIP
--
2.51.0
next prev parent reply other threads:[~2025-09-22 12:55 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-22 12:46 [PATCH v2 00/11] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
2025-09-22 12:46 ` [PATCH v2 01/11] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
2025-09-22 12:46 ` [PATCH v2 02/11] dt-bindings: riscv: Add Nuclei UX900 compatibles Junhui Liu
2025-09-23 19:03 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 03/11] dt-bindings: riscv: Add Anlogic DR1V90 Junhui Liu
2025-09-22 12:46 ` [PATCH v2 04/11] dt-bindings: timer: Add Anlogic DR1V90 CLINT Junhui Liu
2025-09-27 13:59 ` Qingfang Deng
2025-09-28 3:54 ` Junhui Liu
2025-09-22 12:46 ` [PATCH v2 05/11] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC Junhui Liu
2025-09-23 19:06 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 06/11] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart Junhui Liu
2025-09-22 12:46 ` Junhui Liu [this message]
2025-09-23 19:06 ` [PATCH v2 07/11] riscv: Add Anlogic SoC famly Kconfig support Conor Dooley
2025-09-22 12:46 ` [PATCH v2 08/11] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Junhui Liu
2025-09-23 19:08 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 09/11] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Junhui Liu
2025-09-23 19:08 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 10/11] riscv: defconfig: Enable Anlogic SoC Junhui Liu
2025-09-23 19:08 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 11/11] MAINTAINERS: Setup support for Anlogic DR1V90 SoC tree Junhui Liu
2025-09-23 19:09 ` Conor Dooley
2025-09-25 3:06 ` [PATCH v2 00/11] riscv: Add initial support for Anlogic DR1V90 fushan.zeng
2025-09-25 3:49 ` Troy Mitchell
2025-09-25 3:49 ` Krzysztof Kozlowski
2025-09-25 17:09 ` Conor Dooley
2025-09-26 14:38 ` fushan.zeng
2025-09-25 17:22 ` Conor Dooley
2025-09-29 18:46 ` Conor Dooley
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