From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C84B1261B8F; Mon, 22 Sep 2025 20:43:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758573830; cv=none; b=keTGKKgjBGE7g55IWAw+W8U4AOy16NuqlcTlTMjWS1xQA5NzeOk8/PIzn+w+sKWin2eLXphSaWYfl+TG7W5oZdMGbunChDDhpV4IclK5JiwX7UsJvIizVZ8PbGvYI6WLPnTPpjwY8kwe0zd3ThdtwLOj6UxtBjpN/eCedduNOV4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758573830; c=relaxed/simple; bh=Vy80BelxmGUNpFFuDIVKX3KUuEZh7ay4ov/SQneHVHY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=KiQNUqVerouNuc4irdMLQIJIfq8twZtr80zc40Y3862vNW79ZIuXOjIUsi0fgMyMbBlLBJiTWGCYsLb6ItYJT1p252tDf3tl2btmZnkLcjIbjA+suAWj91Un4DXlQ90HpFGFuxeI3Vx44hNQ3JzrRKKlbc8Of2VrmD8Uj8fhVLw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lkxzgKHm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lkxzgKHm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 028A4C4CEF0; Mon, 22 Sep 2025 20:43:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758573830; bh=Vy80BelxmGUNpFFuDIVKX3KUuEZh7ay4ov/SQneHVHY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=lkxzgKHmfF3t4PNAyjogZDoIDiRVy71l18WPbvBAfNwv2BGc8deTkq4LNWRPiL8eW zDazyR61jMG+X8+v9Lvh4Q2vvZ+e0ObpolgRM/HJuS0uRvelPoklqvfwD9yEzwdgfK MHIwcokie9KF92Lo/ihQCLLtxpCi8Sez2G3uKpVQlA+6vTaUrw7Na3Dw3Y+0akxF4b TUjgihjb/ux6nIDi0z5jpKTpCALwwFg6mVQcKpoMrKC0x7ToeivqKafLFVyrtFUKjZ c9uz8OvOXOhQwrhGLNuxqueS879tNh9XZaavay/Khc45zV1JHczBFJzP+NPoLzQ8SS RX64uAZLFGgvA== Date: Mon, 22 Sep 2025 15:43:49 -0500 From: Rob Herring To: Icenowy Zheng Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski , Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 2/8] dt-bindings: display: add verisilicon,dc Message-ID: <20250922204349.GA1290045-robh@kernel.org> References: <20250921083446.790374-1-uwu@icenowy.me> <20250921083446.790374-3-uwu@icenowy.me> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250921083446.790374-3-uwu@icenowy.me> On Sun, Sep 21, 2025 at 04:34:40PM +0800, Icenowy Zheng wrote: > Verisilicon has a series of display controllers prefixed with DC and > with self-identification facility like their GC series GPUs. > > Add a device tree binding for it. > > Depends on the specific DC model, it can have either one or two display > outputs, and each display output could be set to DPI signal or "DP" > signal (which seems to be some plain parallel bus to HDMI controllers). > > Signed-off-by: Icenowy Zheng > --- > Changes in v2: > - Fixed misspelt "versilicon" in title. > - Moved minItems in clock properties to be earlier than items. > - Re-aligned multi-line clocks and resets in example. > > .../bindings/display/verisilicon,dc.yaml | 127 ++++++++++++++++++ > 1 file changed, 127 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > new file mode 100644 > index 0000000000000..07fedc4c7cc13 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > @@ -0,0 +1,127 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Verisilicon DC-series display controllers > + > +maintainers: > + - Icenowy Zheng > + > +properties: > + $nodename: > + pattern: "^display@[0-9a-f]+$" > + > + compatible: > + const: verisilicon,dc This needs an SoC specific compatible. Generally licensed IP compatibles are useless because the specs aren't public and there's always integration quirks. > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + minItems: 4 > + items: > + - description: DC Core clock > + - description: DMA AXI bus clock > + - description: Configuration AHB bus clock > + - description: Pixel clock of output 0 > + - description: Pixel clock of output 1 > + > + clock-names: > + minItems: 4 > + items: > + - const: core > + - const: axi > + - const: ahb > + - const: pix0 > + - const: pix1 > + > + resets: > + items: > + - description: DC Core reset > + - description: DMA AXI bus reset > + - description: Configuration AHB bus reset > + > + reset-names: > + items: > + - const: core > + - const: axi > + - const: ahb > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: The first output channel, endpoint 0 should be > + used for DPI format output and endpoint 1 should be used > + for DP format output. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: The second output channel if the DC variant > + supports and used. Follow the same endpoint addressing > + rule with the first port. > + > + required: > + - port@0 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + display@ffef600000 { > + compatible = "verisilicon,dc"; > + reg = <0xff 0xef600000 0x0 0x100000>; > + interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk_vo CLK_DPU_CCLK>, > + <&clk_vo CLK_DPU_ACLK>, > + <&clk_vo CLK_DPU_HCLK>, > + <&clk_vo CLK_DPU_PIXELCLK0>, > + <&clk_vo CLK_DPU_PIXELCLK1>; > + clock-names = "core", "axi", "ahb", "pix0", "pix1"; > + resets = <&rst TH1520_RESET_ID_DPU_CORE>, > + <&rst TH1520_RESET_ID_DPU_AXI>, > + <&rst TH1520_RESET_ID_DPU_AHB>; > + reset-names = "core", "axi", "ahb"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + }; > + > + port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + dpu_out_dp1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&hdmi_in>; > + }; > + }; > + }; > + }; > + }; > -- > 2.51.0 >