* [PATCH 1/9] dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd.
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
@ 2025-09-23 6:10 ` Albert Yang
2025-09-23 6:10 ` [PATCH 2/9] dt-bindings: arm: add Black Sesame Technologies (bst) SoC Albert Yang
` (8 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-09-23 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc,
Albert Yang
Black Sesame Technologies Co., Ltd.s a leading automotive-grade
computing SoC and SoC-based intelligent vehicle solution provider.
Link: https://bst.ai/.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
Changes for v4:
- adjust ^bst to the correct order
- adjust Acked-by order
Changes for v3:
- No changes
Changes for v2:
- No changes
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 9ec8947dfcad2fa53b2dca2ca06a63710771a600..084ba39016ae23150dd8f140da16f9b1cd55f4cf 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -243,6 +243,8 @@ patternProperties:
description: Shanghai Broadmobi Communication Technology Co.,Ltd.
"^bsh,.*":
description: BSH Hausgeraete GmbH
+ "^bst,.*":
+ description: Black Sesame Technologies Co., Ltd.
"^bticino,.*":
description: Bticino International
"^buffalo,.*":
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 2/9] dt-bindings: arm: add Black Sesame Technologies (bst) SoC
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
2025-09-23 6:10 ` [PATCH 1/9] dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd Albert Yang
@ 2025-09-23 6:10 ` Albert Yang
2025-09-23 6:10 ` [PATCH 3/9] arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs Albert Yang
` (7 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-09-23 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc,
Albert Yang, Krzysztof Kozlowski
Add device tree bindings for Black Sesame Technologies Arm SoC,
it consists several SoC models like C1200, etc.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes for v4:
- remove Signed-off-by: Ge Gordon
- add Reviewed-by Krzysztof Kozlowski info
Changes for v3:
- Add Signed-off-by: Ge Gordon
Changes for v2:
- Removed unnecessary pipe (`|`) in description
- Dropped invalid `compatible` entry for standalone SoC
- Removed root node (`$nodename: '/'`) definition
---
Documentation/devicetree/bindings/arm/bst.yaml | 31 ++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/bst.yaml b/Documentation/devicetree/bindings/arm/bst.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..a3a7f424fd57f23efeed9b076c2612ba672be3e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bst.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: BST platforms
+
+description:
+ Black Sesame Technologies (BST) is a semiconductor company that produces
+ automotive-grade system-on-chips (SoCs) for intelligent driving, focusing
+ on computer vision and AI capabilities. The BST C1200 family includes SoCs
+ for ADAS (Advanced Driver Assistance Systems) and autonomous driving
+ applications.
+
+maintainers:
+ - Ge Gordon <gordon.ge@bst.ai>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: BST C1200 CDCU1.0 ADAS 4C2G board
+ items:
+ - const: bst,c1200-cdcu1.0-adas-4c2g
+ - const: bst,c1200
+
+additionalProperties: true
+
+...
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 3/9] arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
2025-09-23 6:10 ` [PATCH 1/9] dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd Albert Yang
2025-09-23 6:10 ` [PATCH 2/9] dt-bindings: arm: add Black Sesame Technologies (bst) SoC Albert Yang
@ 2025-09-23 6:10 ` Albert Yang
2025-09-23 6:10 ` [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller Albert Yang
` (6 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-09-23 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc,
Albert Yang
Add ARCH_BST configuration option to enable support for Black Sesame
Technologies SoC family. BST produces automotive-grade system-on-chips
for intelligent driving, focusing on computer vision and AI capabilities.
The BST C1200 family includes SoCs for ADAS and autonomous driving
applications.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
---
Changes for v4:
- remove Signed-off-by: Ge Gordon
Changes for v3:
- Reword subject from "for bst silicons" to "for Black Sesame Technologies
SoCs"
- drop unrelated whitespace hunk
Changes for v2:
- Placed the configuration entry in correct alphabetical order
- Used generic family name (ARCH_BST) instead of SoC-specific naming
- Followed upstream kernel naming and description conventions
---
arch/arm64/Kconfig.platforms | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index a88f5ad9328c2ee13a0822782af6c83899273f14..8a870b213dee930861bab39dce2df295c387cf89 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -112,6 +112,14 @@ config ARCH_BLAIZE
help
This enables support for the Blaize SoC family
+config ARCH_BST
+ bool "Black Sesame Technologies SoC Family"
+ help
+ This enables support for Black Sesame Technologies (BST) SoC family.
+ BST produces automotive-grade system-on-chips for intelligent driving,
+ focusing on computer vision and AI capabilities. The BST C1200 family
+ includes SoCs for ADAS and autonomous driving applications.
+
config ARCH_CIX
bool "Cixtech SoC family"
help
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
` (2 preceding siblings ...)
2025-09-23 6:10 ` [PATCH 3/9] arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs Albert Yang
@ 2025-09-23 6:10 ` Albert Yang
2025-09-23 10:13 ` Rob Herring (Arm)
2025-09-23 13:56 ` Rob Herring
2025-09-23 6:10 ` [PATCH 5/9] mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver Albert Yang
` (5 subsequent siblings)
9 siblings, 2 replies; 25+ messages in thread
From: Albert Yang @ 2025-09-23 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc,
Albert Yang
Add device tree binding documentation for the Black Sesame Technologies
(BST) DWCMSHC SDHCI controller.
This binding describes the required and optional properties for the
bst,c1200-dwcmshc-sdhci compatible controller, including register layout,
interrupts, bus width, clock configuration, and other controller-specific
features.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
---
Changes for v4:
- Remove Signed-off-by line for Ge Gordon
- Change `$ref: mmc-controller.yaml#` to `$ref: sdhci-common.yaml#`
- Change compatible string from `bst,c1200-dwcmshc-sdhci` to `bst,c1200-sdhci`
Changes for v3:
- Switch reg schema from maxItems to explicit items with per-entry descriptions
- Improve example: add irq.h include and wrap under a bus node with address/size cells
- Drop status = "disabled" from example; keep example concise
- Add Signed-off-by: Ge Gordon
Changes for v2:
- Simplify description, remove redundant paragraphs
- Update $schema to reference mmc-specific scheme
- Correct compatible to add soc name (bst,c1200-dwcmshc-sdhci)
- Remove all redundant property descriptions
- Drop invalid mmc_crm_base/size properties, use reg for all address ranges
- Clean up required properties to only essential entries
- Standardize example DTS format, fix reg syntax and property ordering
- Remove additionalProperties: true
---
.../devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..7f16e6db39690cb7621d167bf7bc492f814ea693
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/bst,dwcmshc-sdhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Black Sesame Technologies DWCMSHC SDHCI Controller
+
+maintainers:
+ - Ge Gordon <gordon.ge@bst.ai>
+
+allOf:
+ - $ref: sdhci-common.yaml#
+
+properties:
+ compatible:
+ const: bst,c1200-sdhci
+
+ reg:
+ items:
+ - description: Core SDHCI registers
+ - description: CRM registers
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: core
+
+ memory-region:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mmc@22200000 {
+ compatible = "bst,c1200-dwcmshc-sdhci";
+ reg = <0x0 0x22200000 0x0 0x1000>,
+ <0x0 0x23006000 0x0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_mmc>;
+ clock-names = "core";
+ memory-region = <&mmc0_reserved>;
+ max-frequency = <200000000>;
+ bus-width = <8>;
+ non-removable;
+ dma-coherent;
+ };
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
2025-09-23 6:10 ` [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller Albert Yang
@ 2025-09-23 10:13 ` Rob Herring (Arm)
2025-10-15 9:31 ` Albert Yang
2025-09-23 13:56 ` Rob Herring
1 sibling, 1 reply; 25+ messages in thread
From: Rob Herring (Arm) @ 2025-09-23 10:13 UTC (permalink / raw)
To: Albert Yang
Cc: linux-kernel, devicetree, Ulf Hansson, Will Deacon,
linux-arm-kernel, Conor Dooley, Ge Gordon, Adrian Hunter,
Arnd Bergmann, soc, BST Linux Kernel Upstream Group,
Krzysztof Kozlowski, linux-mmc, Catalin Marinas
On Tue, 23 Sep 2025 14:10:10 +0800, Albert Yang wrote:
> Add device tree binding documentation for the Black Sesame Technologies
> (BST) DWCMSHC SDHCI controller.
>
> This binding describes the required and optional properties for the
> bst,c1200-dwcmshc-sdhci compatible controller, including register layout,
> interrupts, bus width, clock configuration, and other controller-specific
> features.
>
> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
>
> ---
> Changes for v4:
> - Remove Signed-off-by line for Ge Gordon
> - Change `$ref: mmc-controller.yaml#` to `$ref: sdhci-common.yaml#`
> - Change compatible string from `bst,c1200-dwcmshc-sdhci` to `bst,c1200-sdhci`
>
> Changes for v3:
> - Switch reg schema from maxItems to explicit items with per-entry descriptions
> - Improve example: add irq.h include and wrap under a bus node with address/size cells
> - Drop status = "disabled" from example; keep example concise
> - Add Signed-off-by: Ge Gordon
>
> Changes for v2:
> - Simplify description, remove redundant paragraphs
> - Update $schema to reference mmc-specific scheme
> - Correct compatible to add soc name (bst,c1200-dwcmshc-sdhci)
> - Remove all redundant property descriptions
> - Drop invalid mmc_crm_base/size properties, use reg for all address ranges
> - Clean up required properties to only essential entries
> - Standardize example DTS format, fix reg syntax and property ordering
> - Remove additionalProperties: true
> ---
> .../devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml | 70 ++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.example.dtb: /example-0/bus/mmc@22200000: failed to match any schema with compatible: ['bst,c1200-dwcmshc-sdhci']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250923-v4-patch-final-v1-4-2283ad7cbf88@thundersoft.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
2025-09-23 10:13 ` Rob Herring (Arm)
@ 2025-10-15 9:31 ` Albert Yang
0 siblings, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-10-15 9:31 UTC (permalink / raw)
To: robh
Cc: adrian.hunter, arnd, bst-upstream, catalin.marinas, conor+dt,
devicetree, gordon.ge, krzk+dt, linux-kernel, linux-mmc,
ulf.hansson, will, yangzh0906
Hi Rob,
Thank you for running the dt_binding_check on this patch!
On Tue, Sep 23, 2025 at 05:13:09AM -0500, Rob Herring (Arm) wrote:
> My bot found errors running 'make dt_binding_check' on your patch:
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.example.dtb: /example-0/bus/mmc@22200000: failed to match any schema with compatible: ['bst,c1200-dwcmshc-sdhci']
This error occurred because in v4, while I updated the dts compatible property
definition to "bst,c1200-sdhci" (as requested in review), I failed to update
the compatible string in the example node accordingly. The example was still
using the old "bst,c1200-dwcmshc-sdhci", causing the schema validation to fail.
I have now corrected the example's compatible string from:
compatible = "bst,c1200-dwcmshc-sdhci";
to:
compatible = "bst,c1200-sdhci";
Following your suggestion, I've upgraded dtschema:
pip3 install dtschema --upgrade
and verified the fix with:
make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/bst,c1200-sdhci.yaml
The binding now passes all validation checks. This fix will be included in v5.
Best regards,
Albert Yang
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
2025-09-23 6:10 ` [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller Albert Yang
2025-09-23 10:13 ` Rob Herring (Arm)
@ 2025-09-23 13:56 ` Rob Herring
2025-09-26 3:06 ` [PATCH v4 4/9] dt-bindings: mmc: Add Black Sesame Technologies DWCMSHC SDHCI Albert Yang
2025-10-15 9:09 ` [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller Albert Yang
1 sibling, 2 replies; 25+ messages in thread
From: Rob Herring @ 2025-09-23 13:56 UTC (permalink / raw)
To: Albert Yang
Cc: Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann, devicetree,
linux-kernel, linux-arm-kernel, linux-mmc, soc
On Tue, Sep 23, 2025 at 02:10:10PM +0800, Albert Yang wrote:
> Add device tree binding documentation for the Black Sesame Technologies
> (BST) DWCMSHC SDHCI controller.
>
> This binding describes the required and optional properties for the
> bst,c1200-dwcmshc-sdhci compatible controller, including register layout,
> interrupts, bus width, clock configuration, and other controller-specific
> features.
>
> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
>
> ---
> Changes for v4:
Thanks for the changelog here, but the subject should have 'PATCH v4' so
various tools work.
> - Remove Signed-off-by line for Ge Gordon
> - Change `$ref: mmc-controller.yaml#` to `$ref: sdhci-common.yaml#`
> - Change compatible string from `bst,c1200-dwcmshc-sdhci` to `bst,c1200-sdhci`
>
> Changes for v3:
> - Switch reg schema from maxItems to explicit items with per-entry descriptions
> - Improve example: add irq.h include and wrap under a bus node with address/size cells
> - Drop status = "disabled" from example; keep example concise
> - Add Signed-off-by: Ge Gordon
>
> Changes for v2:
> - Simplify description, remove redundant paragraphs
> - Update $schema to reference mmc-specific scheme
> - Correct compatible to add soc name (bst,c1200-dwcmshc-sdhci)
> - Remove all redundant property descriptions
> - Drop invalid mmc_crm_base/size properties, use reg for all address ranges
> - Clean up required properties to only essential entries
> - Standardize example DTS format, fix reg syntax and property ordering
> - Remove additionalProperties: true
> ---
> .../devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml | 70 ++++++++++++++++++++++
Filename should match compatible.
> 1 file changed, 70 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..7f16e6db39690cb7621d167bf7bc492f814ea693
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/bst,dwcmshc-sdhci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Black Sesame Technologies DWCMSHC SDHCI Controller
> +
> +maintainers:
> + - Ge Gordon <gordon.ge@bst.ai>
> +
> +allOf:
> + - $ref: sdhci-common.yaml#
> +
> +properties:
> + compatible:
> + const: bst,c1200-sdhci
> +
> + reg:
> + items:
> + - description: Core SDHCI registers
> + - description: CRM registers
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: core
Not really any point in having -names when there is only 1 entry.
> +
> + memory-region:
> + maxItems: 1
Having this is odd. Please add a description saying what it is for.
> +
> + dma-coherent: true
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mmc@22200000 {
> + compatible = "bst,c1200-dwcmshc-sdhci";
> + reg = <0x0 0x22200000 0x0 0x1000>,
> + <0x0 0x23006000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_mmc>;
> + clock-names = "core";
> + memory-region = <&mmc0_reserved>;
> + max-frequency = <200000000>;
> + bus-width = <8>;
> + non-removable;
> + dma-coherent;
> + };
> + };
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v4 4/9] dt-bindings: mmc: Add Black Sesame Technologies DWCMSHC SDHCI
2025-09-23 13:56 ` Rob Herring
@ 2025-09-26 3:06 ` Albert Yang
2025-10-15 9:09 ` [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller Albert Yang
1 sibling, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-09-26 3:06 UTC (permalink / raw)
To: robh
Cc: adrian.hunter, arnd, bst-upstream, catalin.marinas, conor+dt,
devicetree, gordon.ge, krzk+dt, linux-arm-kernel, linux-kernel,
linux-mmc, ulf.hansson, will, yangzh0906
On Tue, Sep 23, 2025 at 08:56:20AM -0500, Rob Herring wrote:
> On Tue, Sep 23, 2025 at 02:10:10PM +0800, Albert Yang wrote:
> > Add device tree binding documentation for the Black Sesame Technologies
> > (BST) DWCMSHC SDHCI controller.
Hi Rob,
Thanks for the review.
> Thanks for the changelog here, but the subject should have 'PATCH v4' so
> various tools work.
Understood. Will ensure v5 has the proper subject format with 'PATCH v5'.
> Filename should match compatible.
Fixed. Renamed from bst,dwcmshc-sdhci.yaml to bst,c1200-dwcmshc.yaml
to match the compatible string "bst,c1200-dwcmshc", and updated the
$id field accordingly.
> Not really any point in having -names when there is only 1 entry.
Agreed. I've dropped clock-names from the schema, DTS, and removed it
from required properties.
> Having this is odd. Please add a description saying what it is for.
Added description for memory-region: "Reserved memory region for bounce
buffer. Required due to controller's 32-bit DMA limitation while system
RAM is above 32-bit addressable range."
Updated example:
mmc@22200000 {
compatible = "bst,c1200-dwcmshc";
reg = <0x0 0x22200000 0x0 0x1000>,
<0x0 0x23006000 0x0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_mmc>;
memory-region = <&mmc0_reserved>;
max-frequency = <200000000>;
bus-width = <8>;
non-removable;
dma-coherent;
};
Please let me know if you have any other concerns or suggestions for
this binding. I'll send v5 with these fixes.
Thanks,
Albert Yang
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
2025-09-23 13:56 ` Rob Herring
2025-09-26 3:06 ` [PATCH v4 4/9] dt-bindings: mmc: Add Black Sesame Technologies DWCMSHC SDHCI Albert Yang
@ 2025-10-15 9:09 ` Albert Yang
1 sibling, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-10-15 9:09 UTC (permalink / raw)
To: robh
Cc: adrian.hunter, arnd, bst-upstream, catalin.marinas, conor+dt,
devicetree, gordon.ge, krzk+dt, linux-kernel, linux-mmc,
ulf.hansson, will, yangzh0906
Hi Rob,
Thank you for your review and feedback on v4!
On Tue, Sep 23, 2025 at 08:56:20AM -0500, Rob Herring wrote:
> On Tue, Sep 23, 2025 at 02:10:10PM +0800, Albert Yang wrote:
> > Changes for v4:
>
> Thanks for the changelog here, but the subject should have 'PATCH v4' so
> various tools work.
Acknowledged. I'll ensure the subject line follows the correct format
"[PATCH v5 X/Y]" in the next version.
> Filename should match compatible.
Agreed. I will rename the file from:
bst,dwcmshc-sdhci.yaml
to:
bst,c1200-sdhci.yaml
and update the $id field accordingly from:
http://devicetree.org/schemas/mmc/bst,dwcmshc-sdhci.yaml#
to:
http://devicetree.org/schemas/mmc/bst,c1200-sdhci.yaml#
> > + clock-names:
> > + items:
> > + - const: core
>
> Not really any point in having -names when there is only 1 entry.> Not really any point in having -names when there is only 1 entry.
You're right. I'll remove the clock-names property and its entry from the
required properties list.
> > + memory-region:
> > + maxItems: 1
>
> Having this is odd. Please add a description saying what it is for.
>> Having this is odd. Please add a description saying what it is for.
I'll add a description for memory-region:
memory-region:
maxItems: 1
description:
Phandle to a reserved memory region for DMA bounce buffer. The BST C1200
SDHCI controller supports only 32-bit DMA addressing, while system memory
may be located above 4GB address space.
Additionally, I've already corrected the example's compatible string from
"bst,c1200-dwcmshc-sdhci" to "bst,c1200-sdhci" to match the property definition.
I'll prepare v5 with all the above changes addressed.
Best regards,
Albert Yang
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 5/9] mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
` (3 preceding siblings ...)
2025-09-23 6:10 ` [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller Albert Yang
@ 2025-09-23 6:10 ` Albert Yang
2025-09-29 13:25 ` Adrian Hunter
2025-09-23 6:10 ` [PATCH 6/9] mmc: sdhci: allow drivers to pre-allocate bounce buffer Albert Yang
` (4 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Albert Yang @ 2025-09-23 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc,
Albert Yang
Add SDHCI controller driver for Black Sesame Technologies C1200 SoC.
This driver supports the DWCMSHC SDHCI controller with BST-specific
enhancements including:
- Custom clock management and tuning
- Power management support
- BST-specific register configurations
- Support for eMMC and SD card interfaces
- Hardware limitation workaround for 32-bit DMA addressing
The driver addresses specific hardware constraints where:
- System memory uses 64-bit bus, eMMC controller uses 32-bit bus
- eMMC controller cannot access memory through SMMU due to hardware bug
- All system DRAM is configured outside 4GB boundary (ZONE_DMA32)
- Uses SRAM-based bounce buffer within 32-bit address space
Signed-off-by: Ge Gordon <gordon.ge@bst.ai>
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
Changes for v4:
- Rename all functions from bst_* to sdhci_bst_* for better namespace consistency
- Rename driver file from sdhci-of-bst-c1200.c to sdhci-of-bst.c
- Rename dwcmshc_priv structure to sdhci_bst_priv for clarity
- Update driver name from "sdhci-dwcmshc" to "sdhci-bst" throughout
- Add comprehensive register bit mask definitions and named constants
- Replace manual polling loops with read_poll_timeout() for clock stability
- Add dedicated sdhci_bst_wait_int_clk() function for internal clock management
- Completely rewrite power management with proper power-off handling
- Enhance clock control with read-modify-write operations to avoid clobbering
- Add MBIU burst mode configuration based on power state
- Improve error handling and cleanup in probe/remove functions
- Simplify bounce buffer allocation and remove redundant MMC parameter adjustments
- Add SDHCI_QUIRK_BROKEN_ADMA quirk for hardware limitation
- Replace ioread32/iowrite32 with readl/writel for consistency
- Update copyright year and simplify license text
- Improve tuning algorithm with clearer variable naming
- Enhance register access patterns with proper bit field manipulation
- Add power-off clock management to reduce idle power consumption
- Add Acked-by: Arnd Bergmann
Changes for v3:
- Simplify dwcmshc_priv structure by removing unused fields
- Improve helper functions with better encapsulation
- Use devm_platform_ioremap_resource() for resource management
- Update Kconfig description and alphabetical ordering
- Clarify documentation on hardware limitations and bounce buffer approach
- Remove duplicate sdhci_writew SDHCI_CLOCK_CONTROL
Changes for v2:
- Remove COMMON_CLK dependency from Kconfig (MMC_SDHCI_BST)
- Add ARCH_BST || COMPILE_TEST dependency from Kconfig (MMC_SDHCI_BST)
- Replace temporary ioremap with persistent mapping
- Map CRM registers once during probe instead of per-access
- Add proper cleanup in remove callback
- Refactor bounce buffer allocation with simplified error handling
- Remove unnecessary DMA configuration layers
- Prune unused headers and legacy vendor debug code
- Remove deprecated sdhci_bst_print_vendor() export
- Convert internal functions to static scope
- Standardize naming conventions (DRIVER_NAME, DEFAULT_MAX_FREQ)
- Optimize clock configuration routines
- Fix register access macros for EMMC_CTRL with proper offset calculation
- Correct device tree compatibility string to "bst,c1200-dwcmshc-sdhci"
- Add robust ioremap error checking
- Improve bounce buffer allocation failure handling
- Update MODULE_DESCRIPTION and AUTHOR fields
- Add explanatory comments for hardware limitations
- Remove redundant multi-host setup infrastructure
- Fix build warnings from lkp (kernel test robot)
---
drivers/mmc/host/Kconfig | 14 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-of-bst.c | 544 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 559 insertions(+)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 7232de1c068873d9bccec0b3b43ece939cb84894..75c37be559d23bff773bbe3f018b76c34ad710ca 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -429,6 +429,20 @@ config MMC_SDHCI_BCM_KONA
If you have a controller with this interface, say Y or M here.
+config MMC_SDHCI_BST
+ tristate "SDHCI support for Black Sesame Technologies BST C1200 controller"
+ depends on ARCH_BST || COMPILE_TEST
+ depends on MMC_SDHCI_PLTFM
+ depends on OF
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ for Black Sesame Technologies BST C1200 SoC. The controller is
+ based on Synopsys DesignWare Cores Mobile Storage Controller but
+ requires platform-specific workarounds for hardware limitations.
+
+ If you have a controller with this interface, say Y or M here.
+ If unsure, say N.
+
config MMC_SDHCI_F_SDH30
tristate "SDHCI support for Fujitsu Semiconductor F_SDH30"
depends on MMC_SDHCI_PLTFM
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 5057fea8afb696e210e465a6a2aafc68adad7854..ee412e6b84d6c91f80654e53d0a05b549d4b6171 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_UHS2) += sdhci-uhs2.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
+obj-$(CONFIG_MMC_SDHCI_BST) += sdhci-of-bst.o
sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \
sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
diff --git a/drivers/mmc/host/sdhci-of-bst.c b/drivers/mmc/host/sdhci-of-bst.c
new file mode 100644
index 0000000000000000000000000000000000000000..b19b763f216a25f58d37c8e288a8aa791f1e20f7
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of-bst.c
@@ -0,0 +1,544 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SDHCI driver for Black Sesame Technologies C1200 controller
+ *
+ * Copyright (c) 2025 Black Sesame Technologies
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+#include <linux/iopoll.h>
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+
+/* SDHCI standard register extensions */
+#define SDHCI_CLOCK_PLL_EN 0x0008
+#define SDHCI_TUNING_COUNT 0x20
+#define SDHCI_VENDOR_PTR_R 0xE8
+
+/* Synopsys vendor specific registers */
+#define SDHC_EMMC_CTRL_R_OFFSET 0x2C
+#define MBIU_CTRL 0x510
+
+/* MBIU burst control bits */
+#define BURST_INCR16_EN BIT(3)
+#define BURST_INCR8_EN BIT(2)
+#define BURST_INCR4_EN BIT(1)
+#define BURST_EN (BURST_INCR16_EN | BURST_INCR8_EN | BURST_INCR4_EN)
+#define MBIU_BURST_MASK GENMASK(3, 0)
+
+/* CRM (Clock/Reset/Management) register offsets */
+#define SDEMMC_CRM_BCLK_DIV_CTRL 0x08
+#define SDEMMC_CRM_TIMER_DIV_CTRL 0x0C
+#define SDEMMC_CRM_RX_CLK_CTRL 0x14
+#define SDEMMC_CRM_VOL_CTRL 0x1C
+#define REG_WR_PROTECT 0x88
+#define DELAY_CHAIN_SEL 0x94
+
+/* CRM register values and bit definitions */
+#define REG_WR_PROTECT_KEY 0x1234abcd
+#define BST_VOL_STABLE_ON BIT(7)
+#define BST_TIMER_DIV_MASK GENMASK(7, 0)
+#define BST_TIMER_DIV_VAL 0x20
+#define BST_TIMER_LOAD_BIT BIT(8)
+#define BST_BCLK_EN_BIT BIT(10)
+#define BST_RX_UPDATE_BIT BIT(11)
+#define BST_EMMC_CTRL_BIT2 BIT(2)
+
+/* Clock frequency limits */
+#define BST_DEFAULT_MAX_FREQ 2000000UL
+#define BST_DEFAULT_MIN_FREQ 400000UL
+
+/* Clock control bit definitions */
+#define BST_CLOCK_DIV_MASK GENMASK(7, 0)
+#define BST_CLOCK_DIV_SHIFT 8
+#define BST_BCLK_DIV_MASK GENMASK(9, 0)
+
+/* Clock frequency thresholds */
+#define BST_CLOCK_THRESHOLD_LOW 1500
+
+/* Clock stability polling parameters */
+#define BST_CLK_STABLE_POLL_US 1000 /* Poll interval in microseconds */
+#define BST_CLK_STABLE_TIMEOUT_US 20000 /* Timeout for internal clock stabilization (us) */
+
+struct sdhci_bst_priv {
+ void __iomem *crm_reg_base;
+};
+
+union sdhci_bst_rx_ctrl {
+ struct {
+ u32 rx_revert:1,
+ rx_clk_sel_sec:1,
+ rx_clk_div:4,
+ rx_clk_phase_inner:2,
+ rx_clk_sel_first:1,
+ rx_clk_phase_out:2,
+ rx_clk_en:1,
+ res0:20;
+ };
+ u32 reg;
+};
+
+static u32 sdhci_bst_crm_read(struct sdhci_pltfm_host *pltfm_host, u32 offset)
+{
+ struct sdhci_bst_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+ return readl(priv->crm_reg_base + offset);
+}
+
+static void sdhci_bst_crm_write(struct sdhci_pltfm_host *pltfm_host, u32 offset, u32 value)
+{
+ struct sdhci_bst_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+ writel(value, priv->crm_reg_base + offset);
+}
+
+static int sdhci_bst_wait_int_clk(struct sdhci_host *host)
+{
+ u16 clk;
+
+ if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
+ BST_CLK_STABLE_POLL_US, BST_CLK_STABLE_TIMEOUT_US, false,
+ host, SDHCI_CLOCK_CONTROL))
+ return -EBUSY;
+ return 0;
+}
+
+static unsigned int sdhci_bst_get_max_clock(struct sdhci_host *host)
+{
+ return BST_DEFAULT_MAX_FREQ;
+}
+
+static unsigned int sdhci_bst_get_min_clock(struct sdhci_host *host)
+{
+ return BST_DEFAULT_MIN_FREQ;
+}
+
+static void sdhci_bst_enable_clk(struct sdhci_host *host, unsigned int clk)
+{
+ struct sdhci_pltfm_host *pltfm_host;
+ unsigned int div;
+ u32 val;
+ union sdhci_bst_rx_ctrl rx_reg;
+
+ pltfm_host = sdhci_priv(host);
+ if (clk == 0) {
+ div = clk;
+ } else if (clk > BST_DEFAULT_MAX_FREQ) {
+ div = clk / 1000;
+ div = BST_DEFAULT_MAX_FREQ / div;
+ } else if (clk < BST_CLOCK_THRESHOLD_LOW) {
+ div = clk;
+ } else {
+ div = BST_DEFAULT_MAX_FREQ * 100;
+ div = div / clk;
+ div /= 100;
+ }
+
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ clk &= ~SDHCI_CLOCK_PLL_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
+ val &= ~BST_TIMER_LOAD_BIT;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
+
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
+ val &= ~BST_TIMER_DIV_MASK;
+ val |= BST_TIMER_DIV_VAL;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
+
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
+ val |= BST_TIMER_LOAD_BIT;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
+
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
+ val &= ~BST_RX_UPDATE_BIT;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
+
+ rx_reg.reg = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
+
+ rx_reg.rx_revert = 0;
+ rx_reg.rx_clk_sel_sec = 1;
+ rx_reg.rx_clk_div = 4;
+ rx_reg.rx_clk_phase_inner = 2;
+ rx_reg.rx_clk_sel_first = 0;
+ rx_reg.rx_clk_phase_out = 2;
+
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, rx_reg.reg);
+
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
+ val |= BST_RX_UPDATE_BIT;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
+
+ /* Disable clock first */
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
+ val &= ~BST_BCLK_EN_BIT;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
+
+ /* Setup clock divider */
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
+ val &= ~BST_BCLK_DIV_MASK;
+ val |= div;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
+
+ /* Enable clock */
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
+ val |= BST_BCLK_EN_BIT;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
+
+ /* RMW the clock divider bits to avoid clobbering other fields */
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~(BST_CLOCK_DIV_MASK << BST_CLOCK_DIV_SHIFT);
+ clk |= (div & BST_CLOCK_DIV_MASK) << BST_CLOCK_DIV_SHIFT;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk |= SDHCI_CLOCK_PLL_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ clk |= SDHCI_CLOCK_INT_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+}
+
+static void sdhci_bst_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ /* Turn off card/internal/PLL clocks when clock==0 to avoid idle power */
+ u32 clk_reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+
+ if (!clock) {
+ clk_reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_PLL_EN);
+ sdhci_writew(host, clk_reg, SDHCI_CLOCK_CONTROL);
+ return;
+ }
+ sdhci_bst_enable_clk(host, clock);
+}
+
+/**
+ * sdhci_bst_reset - Reset the SDHCI host controller
+ * @host: SDHCI host controller
+ * @mask: Reset mask
+ *
+ * Performs a reset of the SDHCI host controller with special handling for eMMC.
+ */
+static void sdhci_bst_reset(struct sdhci_host *host, u8 mask)
+{
+ u16 vendor_ptr, emmc_ctrl_reg;
+ u32 reg;
+
+ if (host->mmc->caps2 & MMC_CAP2_NO_SD) {
+ vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R);
+ emmc_ctrl_reg = vendor_ptr + SDHC_EMMC_CTRL_R_OFFSET;
+
+ reg = sdhci_readw(host, emmc_ctrl_reg);
+ reg &= ~BST_EMMC_CTRL_BIT2;
+ sdhci_writew(host, reg, emmc_ctrl_reg);
+ sdhci_reset(host, mask);
+ usleep_range(10, 20);
+ reg = sdhci_readw(host, emmc_ctrl_reg);
+ reg |= BST_EMMC_CTRL_BIT2;
+ sdhci_writew(host, reg, emmc_ctrl_reg);
+ } else {
+ sdhci_reset(host, mask);
+ }
+}
+
+/**
+ * sdhci_bst_set_timeout - Set timeout value for commands
+ * @host: SDHCI host controller
+ * @cmd: MMC command
+ *
+ * Sets the timeout control register to maximum value (0xE).
+ */
+static void sdhci_bst_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
+{
+ sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
+}
+
+/**
+ * sdhci_bst_set_power - Set power mode and voltage
+ * @host: SDHCI host controller
+ * @mode: Power mode to set
+ * @vdd: Voltage to set
+ *
+ * Sets power mode and voltage, also configures MBIU control register.
+ */
+static void sdhci_bst_set_power(struct sdhci_host *host, unsigned char mode,
+ unsigned short vdd)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ u32 reg;
+ u32 val;
+
+ sdhci_set_power(host, mode, vdd);
+
+ if (mode == MMC_POWER_OFF) {
+ /* Disable MBIU burst mode */
+ reg = sdhci_readw(host, MBIU_CTRL);
+ reg &= ~BURST_EN; /* Clear all burst enable bits */
+ sdhci_writew(host, reg, MBIU_CTRL);
+
+ /* Disable CRM BCLK */
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
+ val &= ~BST_BCLK_EN_BIT;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
+
+ /* Disable RX clock */
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
+ val &= ~BST_RX_UPDATE_BIT;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
+
+ /* Turn off voltage stable power */
+ val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_VOL_CTRL);
+ val &= ~BST_VOL_STABLE_ON;
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, val);
+ } else {
+ /* Configure burst mode only when powered on */
+ reg = sdhci_readw(host, MBIU_CTRL);
+ reg &= ~MBIU_BURST_MASK; /* Clear burst related bits */
+ reg |= BURST_EN; /* Enable burst mode for better bandwidth */
+ sdhci_writew(host, reg, MBIU_CTRL);
+ }
+}
+
+/**
+ * sdhci_bst_execute_tuning - Execute tuning procedure
+ * @host: SDHCI host controller
+ * @opcode: Opcode to use for tuning
+ *
+ * Performs tuning procedure by trying different values and selecting the best one.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int sdhci_bst_execute_tuning(struct sdhci_host *host, u32 opcode)
+{
+ struct sdhci_pltfm_host *pltfm_host;
+ int ret = 0, error;
+ int first_start = -1, first_end = -1, best = 0;
+ int second_start = -1, second_end = -1, has_failure = 0;
+ int i;
+
+ pltfm_host = sdhci_priv(host);
+
+ for (i = 0; i < SDHCI_TUNING_COUNT; i++) {
+ /* Protected write */
+ sdhci_bst_crm_write(pltfm_host, REG_WR_PROTECT, REG_WR_PROTECT_KEY);
+ /* Write tuning value */
+ sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << i) - 1);
+
+ /* Wait for internal clock stable before tuning */
+ if (sdhci_bst_wait_int_clk(host)) {
+ dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n");
+ return -EBUSY;
+ }
+
+ ret = mmc_send_tuning(host->mmc, opcode, &error);
+ if (ret != 0) {
+ has_failure = 1;
+ } else {
+ if (has_failure == 0) {
+ if (first_start == -1)
+ first_start = i;
+ first_end = i;
+ } else {
+ if (second_start == -1)
+ second_start = i;
+ second_end = i;
+ }
+ }
+ }
+
+ /* Calculate best tuning value */
+ if (first_end - first_start >= second_end - second_start)
+ best = ((first_end - first_start) >> 1) + first_start;
+ else
+ best = ((second_end - second_start) >> 1) + second_start;
+
+ if (best < 0)
+ best = 0;
+
+ sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << best) - 1);
+ /* Confirm internal clock stable after setting best tuning value */
+ if (sdhci_bst_wait_int_clk(host)) {
+ dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n");
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+/**
+ * sdhci_bst_voltage_switch - Perform voltage switch
+ * @host: SDHCI host controller
+ *
+ * Enables voltage stable power.
+ */
+static void sdhci_bst_voltage_switch(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+ /* Enable voltage stable power */
+ sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, BST_VOL_STABLE_ON);
+}
+
+static const struct sdhci_ops sdhci_bst_ops = {
+ .set_clock = sdhci_bst_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ .get_min_clock = sdhci_bst_get_min_clock,
+ .get_max_clock = sdhci_bst_get_max_clock,
+ .reset = sdhci_bst_reset,
+ .set_power = sdhci_bst_set_power,
+ .set_timeout = sdhci_bst_set_timeout,
+ .platform_execute_tuning = sdhci_bst_execute_tuning,
+ .voltage_switch = sdhci_bst_voltage_switch,
+};
+
+static const struct sdhci_pltfm_data sdhci_bst_pdata = {
+ .ops = &sdhci_bst_ops,
+ .quirks = SDHCI_QUIRK_BROKEN_ADMA |
+ SDHCI_QUIRK_DELAY_AFTER_POWER |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+ SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
+ .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50 |
+ SDHCI_QUIRK2_TUNING_WORK_AROUND |
+ SDHCI_QUIRK2_ACMD23_BROKEN,
+};
+
+static int sdhci_bst_alloc_bounce_buffer(struct sdhci_host *host)
+{
+ struct mmc_host *mmc = host->mmc;
+ unsigned int bounce_size;
+ int ret;
+
+ /* Fixed SRAM bounce size to 32KB: verified config under 32-bit DMA addressing limit */
+ bounce_size = SZ_32K;
+
+ ret = of_reserved_mem_device_init_by_idx(mmc_dev(mmc), mmc_dev(mmc)->of_node, 0);
+ if (ret) {
+ dev_err(mmc_dev(mmc), "Failed to initialize reserved memory\n");
+ return ret;
+ }
+
+ host->bounce_buffer = dma_alloc_coherent(mmc_dev(mmc), bounce_size,
+ &host->bounce_addr, GFP_KERNEL);
+ if (!host->bounce_buffer)
+ return -ENOMEM;
+
+ host->bounce_buffer_size = bounce_size;
+
+ return 0;
+}
+
+static int sdhci_bst_probe(struct platform_device *pdev)
+{
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_host *host;
+ struct sdhci_bst_priv *priv;
+ int err;
+
+ host = sdhci_pltfm_init(pdev, &sdhci_bst_pdata, sizeof(struct sdhci_bst_priv));
+ if (IS_ERR(host))
+ return PTR_ERR(host);
+
+ pltfm_host = sdhci_priv(host);
+ priv = sdhci_pltfm_priv(pltfm_host); /* Get platform private data */
+
+ err = mmc_of_parse(host->mmc);
+ if (err)
+ return err;
+
+ sdhci_get_of_property(pdev);
+
+ /* Get CRM registers from the second reg entry */
+ priv->crm_reg_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(priv->crm_reg_base)) {
+ err = PTR_ERR(priv->crm_reg_base);
+ return err;
+ }
+
+ /*
+ * Silicon constraints for BST C1200:
+ * - System RAM base is 0x800000000 (above 32-bit addressable range)
+ * - The eMMC controller DMA engine is limited to 32-bit addressing
+ * - SMMU cannot be used on this path due to hardware design flaws
+ * - These are fixed in silicon and cannot be changed in software
+ *
+ * Bus/controller mapping:
+ * - No registers are available to reprogram the address mapping
+ * - The 32-bit DMA limit is a hard constraint of the controller IP
+ *
+ * Given these constraints, an SRAM-based bounce buffer in the 32-bit
+ * address space is required to enable eMMC DMA on this platform.
+ */
+ err = sdhci_bst_alloc_bounce_buffer(host);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to allocate bounce buffer: %d\n", err);
+ return err;
+ }
+
+ err = sdhci_add_host(host);
+ if (err)
+ goto err_free_bounce_buffer;
+
+ return 0;
+
+err_free_bounce_buffer:
+ if (host->bounce_buffer) {
+ dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size,
+ host->bounce_buffer, host->bounce_addr);
+ host->bounce_buffer = NULL;
+ }
+ of_reserved_mem_device_release(mmc_dev(host->mmc));
+
+ return err;
+}
+
+static void sdhci_bst_remove(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+
+ /* Free bounce buffer if allocated */
+ if (host->bounce_buffer) {
+ dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size,
+ host->bounce_buffer, host->bounce_addr);
+ host->bounce_buffer = NULL;
+ }
+
+ /* Release reserved memory */
+ of_reserved_mem_device_release(mmc_dev(host->mmc));
+
+ /* Use platform helper for remove */
+ sdhci_pltfm_remove(pdev);
+}
+
+static const struct of_device_id sdhci_bst_ids[] = {
+ { .compatible = "bst,c1200-dwcmshc-sdhci" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sdhci_bst_ids);
+
+static struct platform_driver sdhci_bst_driver = {
+ .driver = {
+ .name = "sdhci-bst",
+ .of_match_table = sdhci_bst_ids,
+ },
+ .probe = sdhci_bst_probe,
+ .remove = sdhci_bst_remove,
+};
+module_platform_driver(sdhci_bst_driver);
+
+MODULE_DESCRIPTION("Black Sesame Technologies SDHCI driver (BST)");
+MODULE_AUTHOR("Black Sesame Technologies Co., Ltd.");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 5/9] mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver
2025-09-23 6:10 ` [PATCH 5/9] mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver Albert Yang
@ 2025-09-29 13:25 ` Adrian Hunter
0 siblings, 0 replies; 25+ messages in thread
From: Adrian Hunter @ 2025-09-29 13:25 UTC (permalink / raw)
To: Albert Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ge Gordon, BST Linux Kernel Upstream Group, Catalin Marinas,
Will Deacon, Ulf Hansson, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc
On 23/09/2025 09:10, Albert Yang wrote:
> Add SDHCI controller driver for Black Sesame Technologies C1200 SoC.
>
> This driver supports the DWCMSHC SDHCI controller with BST-specific
> enhancements including:
> - Custom clock management and tuning
> - Power management support
> - BST-specific register configurations
> - Support for eMMC and SD card interfaces
> - Hardware limitation workaround for 32-bit DMA addressing
>
> The driver addresses specific hardware constraints where:
> - System memory uses 64-bit bus, eMMC controller uses 32-bit bus
> - eMMC controller cannot access memory through SMMU due to hardware bug
> - All system DRAM is configured outside 4GB boundary (ZONE_DMA32)
> - Uses SRAM-based bounce buffer within 32-bit address space
>
> Signed-off-by: Ge Gordon <gordon.ge@bst.ai>
> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
>
> ---
> Changes for v4:
> - Rename all functions from bst_* to sdhci_bst_* for better namespace consistency
> - Rename driver file from sdhci-of-bst-c1200.c to sdhci-of-bst.c
> - Rename dwcmshc_priv structure to sdhci_bst_priv for clarity
> - Update driver name from "sdhci-dwcmshc" to "sdhci-bst" throughout
> - Add comprehensive register bit mask definitions and named constants
> - Replace manual polling loops with read_poll_timeout() for clock stability
> - Add dedicated sdhci_bst_wait_int_clk() function for internal clock management
> - Completely rewrite power management with proper power-off handling
> - Enhance clock control with read-modify-write operations to avoid clobbering
> - Add MBIU burst mode configuration based on power state
> - Improve error handling and cleanup in probe/remove functions
> - Simplify bounce buffer allocation and remove redundant MMC parameter adjustments
> - Add SDHCI_QUIRK_BROKEN_ADMA quirk for hardware limitation
> - Replace ioread32/iowrite32 with readl/writel for consistency
> - Update copyright year and simplify license text
> - Improve tuning algorithm with clearer variable naming
> - Enhance register access patterns with proper bit field manipulation
> - Add power-off clock management to reduce idle power consumption
> - Add Acked-by: Arnd Bergmann
Thanks for making all these changes. There are a few minor comments
below.
>
> Changes for v3:
> - Simplify dwcmshc_priv structure by removing unused fields
> - Improve helper functions with better encapsulation
> - Use devm_platform_ioremap_resource() for resource management
> - Update Kconfig description and alphabetical ordering
> - Clarify documentation on hardware limitations and bounce buffer approach
> - Remove duplicate sdhci_writew SDHCI_CLOCK_CONTROL
>
> Changes for v2:
> - Remove COMMON_CLK dependency from Kconfig (MMC_SDHCI_BST)
> - Add ARCH_BST || COMPILE_TEST dependency from Kconfig (MMC_SDHCI_BST)
> - Replace temporary ioremap with persistent mapping
> - Map CRM registers once during probe instead of per-access
> - Add proper cleanup in remove callback
> - Refactor bounce buffer allocation with simplified error handling
> - Remove unnecessary DMA configuration layers
> - Prune unused headers and legacy vendor debug code
> - Remove deprecated sdhci_bst_print_vendor() export
> - Convert internal functions to static scope
> - Standardize naming conventions (DRIVER_NAME, DEFAULT_MAX_FREQ)
> - Optimize clock configuration routines
> - Fix register access macros for EMMC_CTRL with proper offset calculation
> - Correct device tree compatibility string to "bst,c1200-dwcmshc-sdhci"
> - Add robust ioremap error checking
> - Improve bounce buffer allocation failure handling
> - Update MODULE_DESCRIPTION and AUTHOR fields
> - Add explanatory comments for hardware limitations
> - Remove redundant multi-host setup infrastructure
> - Fix build warnings from lkp (kernel test robot)
> ---
> drivers/mmc/host/Kconfig | 14 ++
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/sdhci-of-bst.c | 544 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 559 insertions(+)
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 7232de1c068873d9bccec0b3b43ece939cb84894..75c37be559d23bff773bbe3f018b76c34ad710ca 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -429,6 +429,20 @@ config MMC_SDHCI_BCM_KONA
>
> If you have a controller with this interface, say Y or M here.
>
> +config MMC_SDHCI_BST
> + tristate "SDHCI support for Black Sesame Technologies BST C1200 controller"
> + depends on ARCH_BST || COMPILE_TEST
> + depends on MMC_SDHCI_PLTFM
> + depends on OF
> + help
> + This selects the Secure Digital Host Controller Interface (SDHCI)
> + for Black Sesame Technologies BST C1200 SoC. The controller is
> + based on Synopsys DesignWare Cores Mobile Storage Controller but
> + requires platform-specific workarounds for hardware limitations.
> +
> + If you have a controller with this interface, say Y or M here.
> + If unsure, say N.
> +
> config MMC_SDHCI_F_SDH30
> tristate "SDHCI support for Fujitsu Semiconductor F_SDH30"
> depends on MMC_SDHCI_PLTFM
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 5057fea8afb696e210e465a6a2aafc68adad7854..ee412e6b84d6c91f80654e53d0a05b549d4b6171 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
> obj-$(CONFIG_MMC_SDHCI) += sdhci.o
> obj-$(CONFIG_MMC_SDHCI_UHS2) += sdhci-uhs2.o
> obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
> +obj-$(CONFIG_MMC_SDHCI_BST) += sdhci-of-bst.o
This would be better positioned so that it is not between
obj-$(CONFIG_MMC_SDHCI_PCI) and sdhci-pci-y
> sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \
> sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
> obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
> diff --git a/drivers/mmc/host/sdhci-of-bst.c b/drivers/mmc/host/sdhci-of-bst.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..b19b763f216a25f58d37c8e288a8aa791f1e20f7
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-of-bst.c
> @@ -0,0 +1,544 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * SDHCI driver for Black Sesame Technologies C1200 controller
> + *
> + * Copyright (c) 2025 Black Sesame Technologies
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/ioport.h>
Is linux/ioport.h needed?
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_reserved_mem.h>
> +#include <linux/platform_device.h>
> +#include <linux/iopoll.h>
Also:
#include <linux/bits.h>
And if you use FIELD_PREP():
#include <linux/bitfield.h>
> +#include "sdhci.h"
> +#include "sdhci-pltfm.h"
> +
> +/* SDHCI standard register extensions */
> +#define SDHCI_CLOCK_PLL_EN 0x0008
Already defined in sdhci.h
> +#define SDHCI_TUNING_COUNT 0x20
For SD cards the limit is 40. This number seems to be
driver-specific so should be named accordingly e.g.
#define SDHCI_BST_TUNING_COUNT 0x20
> +#define SDHCI_VENDOR_PTR_R 0xE8
> +
> +/* Synopsys vendor specific registers */
> +#define SDHC_EMMC_CTRL_R_OFFSET 0x2C
> +#define MBIU_CTRL 0x510
> +
> +/* MBIU burst control bits */
> +#define BURST_INCR16_EN BIT(3)
> +#define BURST_INCR8_EN BIT(2)
> +#define BURST_INCR4_EN BIT(1)
> +#define BURST_EN (BURST_INCR16_EN | BURST_INCR8_EN | BURST_INCR4_EN)
> +#define MBIU_BURST_MASK GENMASK(3, 0)
> +
> +/* CRM (Clock/Reset/Management) register offsets */
> +#define SDEMMC_CRM_BCLK_DIV_CTRL 0x08
> +#define SDEMMC_CRM_TIMER_DIV_CTRL 0x0C
> +#define SDEMMC_CRM_RX_CLK_CTRL 0x14
> +#define SDEMMC_CRM_VOL_CTRL 0x1C
> +#define REG_WR_PROTECT 0x88
> +#define DELAY_CHAIN_SEL 0x94
> +
> +/* CRM register values and bit definitions */
> +#define REG_WR_PROTECT_KEY 0x1234abcd
> +#define BST_VOL_STABLE_ON BIT(7)
> +#define BST_TIMER_DIV_MASK GENMASK(7, 0)
> +#define BST_TIMER_DIV_VAL 0x20
> +#define BST_TIMER_LOAD_BIT BIT(8)
> +#define BST_BCLK_EN_BIT BIT(10)
> +#define BST_RX_UPDATE_BIT BIT(11)
> +#define BST_EMMC_CTRL_BIT2 BIT(2)
BST_EMMC_CTRL_BIT2 is not a very descriptive name
> +
> +/* Clock frequency limits */
> +#define BST_DEFAULT_MAX_FREQ 2000000UL
2 MHz looks too low?
> +#define BST_DEFAULT_MIN_FREQ 400000UL
> +
> +/* Clock control bit definitions */
> +#define BST_CLOCK_DIV_MASK GENMASK(7, 0)
> +#define BST_CLOCK_DIV_SHIFT 8
Can use just:
#define BST_CLOCK_DIV_MASK GENMASK(15, 8)
and FIELD_PREP() so that BST_CLOCK_DIV_SHIFT is not needed
> +#define BST_BCLK_DIV_MASK GENMASK(9, 0)
> +
> +/* Clock frequency thresholds */
> +#define BST_CLOCK_THRESHOLD_LOW 1500
> +
> +/* Clock stability polling parameters */
> +#define BST_CLK_STABLE_POLL_US 1000 /* Poll interval in microseconds */
> +#define BST_CLK_STABLE_TIMEOUT_US 20000 /* Timeout for internal clock stabilization (us) */
> +
> +struct sdhci_bst_priv {
> + void __iomem *crm_reg_base;
> +};
> +
> +union sdhci_bst_rx_ctrl {
> + struct {
> + u32 rx_revert:1,
> + rx_clk_sel_sec:1,
> + rx_clk_div:4,
> + rx_clk_phase_inner:2,
> + rx_clk_sel_first:1,
> + rx_clk_phase_out:2,
> + rx_clk_en:1,
> + res0:20;
> + };
> + u32 reg;
> +};
> +
> +static u32 sdhci_bst_crm_read(struct sdhci_pltfm_host *pltfm_host, u32 offset)
> +{
> + struct sdhci_bst_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +
> + return readl(priv->crm_reg_base + offset);
> +}
> +
> +static void sdhci_bst_crm_write(struct sdhci_pltfm_host *pltfm_host, u32 offset, u32 value)
> +{
> + struct sdhci_bst_priv *priv = sdhci_pltfm_priv(pltfm_host);
> +
> + writel(value, priv->crm_reg_base + offset);
> +}
> +
> +static int sdhci_bst_wait_int_clk(struct sdhci_host *host)
> +{
> + u16 clk;
> +
> + if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
> + BST_CLK_STABLE_POLL_US, BST_CLK_STABLE_TIMEOUT_US, false,
> + host, SDHCI_CLOCK_CONTROL))
> + return -EBUSY;
> + return 0;
> +}
> +
> +static unsigned int sdhci_bst_get_max_clock(struct sdhci_host *host)
> +{
> + return BST_DEFAULT_MAX_FREQ;
> +}
> +
> +static unsigned int sdhci_bst_get_min_clock(struct sdhci_host *host)
> +{
> + return BST_DEFAULT_MIN_FREQ;
> +}
> +
> +static void sdhci_bst_enable_clk(struct sdhci_host *host, unsigned int clk)
> +{
> + struct sdhci_pltfm_host *pltfm_host;
> + unsigned int div;
> + u32 val;
> + union sdhci_bst_rx_ctrl rx_reg;
> +
> + pltfm_host = sdhci_priv(host);
> + if (clk == 0) {
> + div = clk;
> + } else if (clk > BST_DEFAULT_MAX_FREQ) {
> + div = clk / 1000;
> + div = BST_DEFAULT_MAX_FREQ / div;
> + } else if (clk < BST_CLOCK_THRESHOLD_LOW) {
> + div = clk;
> + } else {
> + div = BST_DEFAULT_MAX_FREQ * 100;
> + div = div / clk;
> + div /= 100;
> + }
> +
> + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> + clk &= ~SDHCI_CLOCK_CARD_EN;
> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> + clk &= ~SDHCI_CLOCK_PLL_EN;
> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
> + val &= ~BST_TIMER_LOAD_BIT;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
> +
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
> + val &= ~BST_TIMER_DIV_MASK;
> + val |= BST_TIMER_DIV_VAL;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
> +
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL);
> + val |= BST_TIMER_LOAD_BIT;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val);
> +
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
> + val &= ~BST_RX_UPDATE_BIT;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
> +
> + rx_reg.reg = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
> +
> + rx_reg.rx_revert = 0;
> + rx_reg.rx_clk_sel_sec = 1;
> + rx_reg.rx_clk_div = 4;
> + rx_reg.rx_clk_phase_inner = 2;
> + rx_reg.rx_clk_sel_first = 0;
> + rx_reg.rx_clk_phase_out = 2;
> +
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, rx_reg.reg);
> +
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
> + val |= BST_RX_UPDATE_BIT;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
> +
> + /* Disable clock first */
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
> + val &= ~BST_BCLK_EN_BIT;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
> +
> + /* Setup clock divider */
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
> + val &= ~BST_BCLK_DIV_MASK;
> + val |= div;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
> +
> + /* Enable clock */
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
> + val |= BST_BCLK_EN_BIT;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
> +
> + /* RMW the clock divider bits to avoid clobbering other fields */
> + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> + clk &= ~(BST_CLOCK_DIV_MASK << BST_CLOCK_DIV_SHIFT);
> + clk |= (div & BST_CLOCK_DIV_MASK) << BST_CLOCK_DIV_SHIFT;
> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> + clk |= SDHCI_CLOCK_PLL_EN;
> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> + clk |= SDHCI_CLOCK_CARD_EN;
> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> + clk |= SDHCI_CLOCK_INT_EN;
> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +}
> +
> +static void sdhci_bst_set_clock(struct sdhci_host *host, unsigned int clock)
> +{
> + /* Turn off card/internal/PLL clocks when clock==0 to avoid idle power */
> + u32 clk_reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
Could be inside the 'if (!clock) {' block e.g.
if (!clock) {
u32 clk_reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> +
> + if (!clock) {
> + clk_reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_PLL_EN);
> + sdhci_writew(host, clk_reg, SDHCI_CLOCK_CONTROL);
> + return;
> + }
> + sdhci_bst_enable_clk(host, clock);
> +}
> +
> +/**
> + * sdhci_bst_reset - Reset the SDHCI host controller
> + * @host: SDHCI host controller
> + * @mask: Reset mask
> + *
> + * Performs a reset of the SDHCI host controller with special handling for eMMC.
> + */
Kernel style is not to put kernel-doc comments on call-back function
implementations.
> +static void sdhci_bst_reset(struct sdhci_host *host, u8 mask)
> +{
> + u16 vendor_ptr, emmc_ctrl_reg;
> + u32 reg;
> +
> + if (host->mmc->caps2 & MMC_CAP2_NO_SD) {
> + vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R);
> + emmc_ctrl_reg = vendor_ptr + SDHC_EMMC_CTRL_R_OFFSET;
> +
> + reg = sdhci_readw(host, emmc_ctrl_reg);
> + reg &= ~BST_EMMC_CTRL_BIT2;
> + sdhci_writew(host, reg, emmc_ctrl_reg);
> + sdhci_reset(host, mask);
> + usleep_range(10, 20);
> + reg = sdhci_readw(host, emmc_ctrl_reg);
> + reg |= BST_EMMC_CTRL_BIT2;
> + sdhci_writew(host, reg, emmc_ctrl_reg);
> + } else {
> + sdhci_reset(host, mask);
> + }
> +}
> +
> +/**
> + * sdhci_bst_set_timeout - Set timeout value for commands
> + * @host: SDHCI host controller
> + * @cmd: MMC command
> + *
> + * Sets the timeout control register to maximum value (0xE).
> + */
Kernel style is not to put kernel-doc comments on call-back function
implementations.
> +static void sdhci_bst_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
> +{
> + sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
> +}
> +
> +/**
> + * sdhci_bst_set_power - Set power mode and voltage
> + * @host: SDHCI host controller
> + * @mode: Power mode to set
> + * @vdd: Voltage to set
> + *
> + * Sets power mode and voltage, also configures MBIU control register.
> + */
Kernel style is not to put kernel-doc comments on call-back function
implementations.
> +static void sdhci_bst_set_power(struct sdhci_host *host, unsigned char mode,
> + unsigned short vdd)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + u32 reg;
> + u32 val;
> +
> + sdhci_set_power(host, mode, vdd);
> +
> + if (mode == MMC_POWER_OFF) {
> + /* Disable MBIU burst mode */
> + reg = sdhci_readw(host, MBIU_CTRL);
> + reg &= ~BURST_EN; /* Clear all burst enable bits */
> + sdhci_writew(host, reg, MBIU_CTRL);
> +
> + /* Disable CRM BCLK */
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL);
> + val &= ~BST_BCLK_EN_BIT;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val);
> +
> + /* Disable RX clock */
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL);
> + val &= ~BST_RX_UPDATE_BIT;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val);
> +
> + /* Turn off voltage stable power */
> + val = sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_VOL_CTRL);
> + val &= ~BST_VOL_STABLE_ON;
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, val);
> + } else {
> + /* Configure burst mode only when powered on */
> + reg = sdhci_readw(host, MBIU_CTRL);
> + reg &= ~MBIU_BURST_MASK; /* Clear burst related bits */
> + reg |= BURST_EN; /* Enable burst mode for better bandwidth */
> + sdhci_writew(host, reg, MBIU_CTRL);
> + }
> +}
> +
> +/**
> + * sdhci_bst_execute_tuning - Execute tuning procedure
> + * @host: SDHCI host controller
> + * @opcode: Opcode to use for tuning
> + *
> + * Performs tuning procedure by trying different values and selecting the best one.
> + *
> + * Return: 0 on success, negative errno on failure
> + */
Kernel style is not to put kernel-doc comments on call-back function
implementations.
> +static int sdhci_bst_execute_tuning(struct sdhci_host *host, u32 opcode)
> +{
> + struct sdhci_pltfm_host *pltfm_host;
> + int ret = 0, error;
> + int first_start = -1, first_end = -1, best = 0;
> + int second_start = -1, second_end = -1, has_failure = 0;
> + int i;
> +
> + pltfm_host = sdhci_priv(host);
> +
> + for (i = 0; i < SDHCI_TUNING_COUNT; i++) {
> + /* Protected write */
> + sdhci_bst_crm_write(pltfm_host, REG_WR_PROTECT, REG_WR_PROTECT_KEY);
> + /* Write tuning value */
> + sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << i) - 1);
> +
> + /* Wait for internal clock stable before tuning */
> + if (sdhci_bst_wait_int_clk(host)) {
> + dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n");
> + return -EBUSY;
> + }
> +
> + ret = mmc_send_tuning(host->mmc, opcode, &error);
> + if (ret != 0) {
> + has_failure = 1;
> + } else {
> + if (has_failure == 0) {
> + if (first_start == -1)
> + first_start = i;
> + first_end = i;
> + } else {
> + if (second_start == -1)
> + second_start = i;
> + second_end = i;
> + }
> + }
> + }
> +
> + /* Calculate best tuning value */
> + if (first_end - first_start >= second_end - second_start)
> + best = ((first_end - first_start) >> 1) + first_start;
> + else
> + best = ((second_end - second_start) >> 1) + second_start;
> +
> + if (best < 0)
> + best = 0;
> +
> + sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << best) - 1);
> + /* Confirm internal clock stable after setting best tuning value */
> + if (sdhci_bst_wait_int_clk(host)) {
> + dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n");
> + return -EBUSY;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * sdhci_bst_voltage_switch - Perform voltage switch
> + * @host: SDHCI host controller
> + *
> + * Enables voltage stable power.
> + */
Kernel style is not to put kernel-doc comments on call-back function
implementations.
> +static void sdhci_bst_voltage_switch(struct sdhci_host *host)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +
> + /* Enable voltage stable power */
> + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, BST_VOL_STABLE_ON);
> +}
> +
> +static const struct sdhci_ops sdhci_bst_ops = {
> + .set_clock = sdhci_bst_set_clock,
> + .set_bus_width = sdhci_set_bus_width,
> + .set_uhs_signaling = sdhci_set_uhs_signaling,
> + .get_min_clock = sdhci_bst_get_min_clock,
> + .get_max_clock = sdhci_bst_get_max_clock,
> + .reset = sdhci_bst_reset,
> + .set_power = sdhci_bst_set_power,
> + .set_timeout = sdhci_bst_set_timeout,
> + .platform_execute_tuning = sdhci_bst_execute_tuning,
> + .voltage_switch = sdhci_bst_voltage_switch,
> +};
> +
> +static const struct sdhci_pltfm_data sdhci_bst_pdata = {
> + .ops = &sdhci_bst_ops,
> + .quirks = SDHCI_QUIRK_BROKEN_ADMA |
> + SDHCI_QUIRK_DELAY_AFTER_POWER |
> + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> + SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
> + .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50 |
> + SDHCI_QUIRK2_TUNING_WORK_AROUND |
> + SDHCI_QUIRK2_ACMD23_BROKEN,
> +};
> +
> +static int sdhci_bst_alloc_bounce_buffer(struct sdhci_host *host)
> +{
> + struct mmc_host *mmc = host->mmc;
> + unsigned int bounce_size;
> + int ret;
> +
> + /* Fixed SRAM bounce size to 32KB: verified config under 32-bit DMA addressing limit */
> + bounce_size = SZ_32K;
> +
> + ret = of_reserved_mem_device_init_by_idx(mmc_dev(mmc), mmc_dev(mmc)->of_node, 0);
> + if (ret) {
> + dev_err(mmc_dev(mmc), "Failed to initialize reserved memory\n");
> + return ret;
> + }
> +
> + host->bounce_buffer = dma_alloc_coherent(mmc_dev(mmc), bounce_size,
> + &host->bounce_addr, GFP_KERNEL);
> + if (!host->bounce_buffer)
> + return -ENOMEM;
> +
> + host->bounce_buffer_size = bounce_size;
> +
> + return 0;
> +}
> +
> +static int sdhci_bst_probe(struct platform_device *pdev)
> +{
> + struct sdhci_pltfm_host *pltfm_host;
> + struct sdhci_host *host;
> + struct sdhci_bst_priv *priv;
> + int err;
> +
> + host = sdhci_pltfm_init(pdev, &sdhci_bst_pdata, sizeof(struct sdhci_bst_priv));
> + if (IS_ERR(host))
> + return PTR_ERR(host);
> +
> + pltfm_host = sdhci_priv(host);
> + priv = sdhci_pltfm_priv(pltfm_host); /* Get platform private data */
> +
> + err = mmc_of_parse(host->mmc);
> + if (err)
> + return err;
> +
> + sdhci_get_of_property(pdev);
> +
> + /* Get CRM registers from the second reg entry */
> + priv->crm_reg_base = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(priv->crm_reg_base)) {
> + err = PTR_ERR(priv->crm_reg_base);
> + return err;
> + }
> +
> + /*
> + * Silicon constraints for BST C1200:
> + * - System RAM base is 0x800000000 (above 32-bit addressable range)
> + * - The eMMC controller DMA engine is limited to 32-bit addressing
> + * - SMMU cannot be used on this path due to hardware design flaws
> + * - These are fixed in silicon and cannot be changed in software
> + *
> + * Bus/controller mapping:
> + * - No registers are available to reprogram the address mapping
> + * - The 32-bit DMA limit is a hard constraint of the controller IP
> + *
> + * Given these constraints, an SRAM-based bounce buffer in the 32-bit
> + * address space is required to enable eMMC DMA on this platform.
> + */
> + err = sdhci_bst_alloc_bounce_buffer(host);
> + if (err) {
> + dev_err(&pdev->dev, "Failed to allocate bounce buffer: %d\n", err);
> + return err;
> + }
> +
> + err = sdhci_add_host(host);
> + if (err)
> + goto err_free_bounce_buffer;
> +
> + return 0;
> +
> +err_free_bounce_buffer:
> + if (host->bounce_buffer) {
> + dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size,
> + host->bounce_buffer, host->bounce_addr);
> + host->bounce_buffer = NULL;
> + }
> + of_reserved_mem_device_release(mmc_dev(host->mmc));
> +
> + return err;
> +}
> +
> +static void sdhci_bst_remove(struct platform_device *pdev)
> +{
> + struct sdhci_host *host = platform_get_drvdata(pdev);
> +
> + /* Free bounce buffer if allocated */
> + if (host->bounce_buffer) {
> + dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size,
> + host->bounce_buffer, host->bounce_addr);
> + host->bounce_buffer = NULL;
> + }
Same 5 lines of code further above. Could be a separate little helper function.
> +
> + /* Release reserved memory */
> + of_reserved_mem_device_release(mmc_dev(host->mmc));
> +
> + /* Use platform helper for remove */
> + sdhci_pltfm_remove(pdev);
> +}
> +
> +static const struct of_device_id sdhci_bst_ids[] = {
> + { .compatible = "bst,c1200-dwcmshc-sdhci" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, sdhci_bst_ids);
> +
> +static struct platform_driver sdhci_bst_driver = {
> + .driver = {
> + .name = "sdhci-bst",
> + .of_match_table = sdhci_bst_ids,
> + },
> + .probe = sdhci_bst_probe,
> + .remove = sdhci_bst_remove,
> +};
> +module_platform_driver(sdhci_bst_driver);
> +
> +MODULE_DESCRIPTION("Black Sesame Technologies SDHCI driver (BST)");
> +MODULE_AUTHOR("Black Sesame Technologies Co., Ltd.");
> +MODULE_LICENSE("GPL");
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 6/9] mmc: sdhci: allow drivers to pre-allocate bounce buffer
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
` (4 preceding siblings ...)
2025-09-23 6:10 ` [PATCH 5/9] mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver Albert Yang
@ 2025-09-23 6:10 ` Albert Yang
2025-09-29 13:26 ` Adrian Hunter
2025-09-23 6:10 ` [PATCH 7/9] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board Albert Yang
` (3 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Albert Yang @ 2025-09-23 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc,
Albert Yang
In sdhci_allocate_bounce_buffer(), add an early path that respects a
driver-provided pre-allocated bounce buffer (host->bounce_buffer).
If the buffer is already allocated by the driver (e.g. coherent/SRAM
buffer needed for platforms with 32-bit DMA constraints), just compute
max_blocks from host->bounce_buffer_size and jump to the common "out"
path to set mmc->max_*.
This enables platform drivers to allocate the bounce buffer before
sdhci_add_host(), avoiding starting the host without the buffer ready
and aligning with the guidance from review.
No functional change for drivers that do not pre-allocate the buffer.
drivers/mmc/host/sdhci.c (sdhci_allocate_bounce_buffer): Handle
pre-allocated bounce buffer and fall through to set mmc->max_*.
Suggested-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/lkml/2b23bcb9-abc7-4667-b939-a19ecae935a2@intel.com/
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
---
Changes for v4:
- Add new patch by Suggested-by: Adrian Hunter
---
drivers/mmc/host/sdhci.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 3a17821efa5ca92c6c29141d8fcb9ebf58355cc7..03fbe30cb205e16b924481caa44f0979d230f380 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -4193,6 +4193,12 @@ static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
unsigned int bounce_size;
int ret;
+ /* Drivers may have already allocated the buffer */
+ if (host->bounce_buffer) {
+ bounce_size = host->bounce_buffer_size;
+ max_blocks = bounce_size / 512;
+ goto out;
+ }
/*
* Cap the bounce buffer at 64KB. Using a bigger bounce buffer
* has diminishing returns, this is probably because SD/MMC
@@ -4241,6 +4247,7 @@ static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
host->bounce_buffer_size = bounce_size;
+out:
/* Lie about this since we're bouncing */
mmc->max_segs = max_blocks;
mmc->max_seg_size = bounce_size;
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 6/9] mmc: sdhci: allow drivers to pre-allocate bounce buffer
2025-09-23 6:10 ` [PATCH 6/9] mmc: sdhci: allow drivers to pre-allocate bounce buffer Albert Yang
@ 2025-09-29 13:26 ` Adrian Hunter
0 siblings, 0 replies; 25+ messages in thread
From: Adrian Hunter @ 2025-09-29 13:26 UTC (permalink / raw)
To: Albert Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ge Gordon, BST Linux Kernel Upstream Group, Catalin Marinas,
Will Deacon, Ulf Hansson, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc
On 23/09/2025 09:10, Albert Yang wrote:
> In sdhci_allocate_bounce_buffer(), add an early path that respects a
> driver-provided pre-allocated bounce buffer (host->bounce_buffer).
>
> If the buffer is already allocated by the driver (e.g. coherent/SRAM
> buffer needed for platforms with 32-bit DMA constraints), just compute
> max_blocks from host->bounce_buffer_size and jump to the common "out"
> path to set mmc->max_*.
>
> This enables platform drivers to allocate the bounce buffer before
> sdhci_add_host(), avoiding starting the host without the buffer ready
> and aligning with the guidance from review.
>
> No functional change for drivers that do not pre-allocate the buffer.
>
> drivers/mmc/host/sdhci.c (sdhci_allocate_bounce_buffer): Handle
> pre-allocated bounce buffer and fall through to set mmc->max_*.
>
> Suggested-by: Adrian Hunter <adrian.hunter@intel.com>
> Link: https://lore.kernel.org/lkml/2b23bcb9-abc7-4667-b939-a19ecae935a2@intel.com/
> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
This patch needs to come before patch 5 because patch 5 depends on it.
Otherwise:
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
> ---
> Changes for v4:
> - Add new patch by Suggested-by: Adrian Hunter
> ---
> drivers/mmc/host/sdhci.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 3a17821efa5ca92c6c29141d8fcb9ebf58355cc7..03fbe30cb205e16b924481caa44f0979d230f380 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -4193,6 +4193,12 @@ static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
> unsigned int bounce_size;
> int ret;
>
> + /* Drivers may have already allocated the buffer */
> + if (host->bounce_buffer) {
> + bounce_size = host->bounce_buffer_size;
> + max_blocks = bounce_size / 512;
> + goto out;
> + }
> /*
> * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
> * has diminishing returns, this is probably because SD/MMC
> @@ -4241,6 +4247,7 @@ static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
>
> host->bounce_buffer_size = bounce_size;
>
> +out:
> /* Lie about this since we're bouncing */
> mmc->max_segs = max_blocks;
> mmc->max_seg_size = bounce_size;
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 7/9] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
` (5 preceding siblings ...)
2025-09-23 6:10 ` [PATCH 6/9] mmc: sdhci: allow drivers to pre-allocate bounce buffer Albert Yang
@ 2025-09-23 6:10 ` Albert Yang
2025-09-23 6:10 ` [PATCH 8/9] arm64: defconfig: enable BST platform and SDHCI controller support Albert Yang
` (2 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-09-23 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc,
Albert Yang
Add device tree support for the Black Sesame Technologies (BST) C1200
CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC
family.
The changes include:
- Adding a new BST device tree directory
- Adding Makefile entries to build the BST platform device trees
- Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board
This board features a quad-core Cortex-A78 CPU, and various peripherals
including UART, MMC, watchdog timer, and interrupt controller.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
---
Changes for v4:
- Remove Signed-off-by line for Ge Gordon
- Reorder device tree node properties for better consistency
- CPU nodes: move `device_type` before `compatible`, add explicit `reg` values
- MMC node: change compatible from `bst,c1200-dwcmshc-sdhci` to `bst,c1200-sdhci`
- MMC node: remove `bus-width` and `non-removable` from SoC dtsi, move to board dts
- SoC node: reorder properties (`ranges` before address/size cells)
- UART node: reorder properties (clock-frequency before interrupts)
- GIC node: reorder properties for better readability
- Timer node: reorder properties (always-on before interrupt-parent)
- Board DTS: add `bus-width = <8>` and `non-removable` to MMC node
- Board DTS: reorder MMC and UART node references
Changes for v3:
- Split defconfig enablement out into a dedicated defconfig patch
- Refine memory description: consolidate ranges in memory node and delete unused memory ranges
- Adjust the order of nodes
- Remove mask of gic
Changes for v2:
- Reorganize memory map into discrete regions
- Update MMC controller definition with split core/CRM register regions
- Remove deprecated properties
- Update compatible string
- Standardize interrupt definitions and numeric formats
- Remove reserved-memory node (superseded by bounce buffers)
- Add root compatible string for platform identification
- Add soc defconfig
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/bst/Makefile | 2 +
.../boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 43 ++++++++
arch/arm64/boot/dts/bst/bstc1200.dtsi | 115 +++++++++++++++++++++
4 files changed, 161 insertions(+)
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index b0844404eda1835d7f3112a1250dde74ac251c50..98ec8f1b76e4753257e8678c6db918053e9c528d 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -13,6 +13,7 @@ subdir-y += axiado
subdir-y += bitmain
subdir-y += blaize
subdir-y += broadcom
+subdir-y += bst
subdir-y += cavium
subdir-y += cix
subdir-y += exynos
diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..4c1b8b4cdad893df0cc47d81a64d9cbc7a60a9dd
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb
diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
new file mode 100644
index 0000000000000000000000000000000000000000..178ad4bf4f0aacf831a61af07ad151a70e075749
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "bstc1200.dtsi"
+
+/ {
+ model = "BST C1200-96 CDCU1.0 4C2G";
+ compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@810000000 {
+ device_type = "memory";
+ reg = <0x8 0x10000000 0x0 0x30000000>,
+ <0x8 0xc0000000 0x1 0x0>,
+ <0xc 0x00000000 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mmc0_reserved: mmc0-reserved@5160000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x5160000 0x0 0x10000>;
+ no-map;
+ };
+ };
+};
+
+&mmc0 {
+ bus-width = <8>;
+ memory-region = <&mmc0_reserved>;
+ non-removable;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..9660d8396e275945b27846c80dde79478c16ae76
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "bst,c1200";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clk_mmc: clock-4000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ uart0: serial@20008000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20008000 0x0 0x1000>;
+ clock-frequency = <25000000>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@22200000 {
+ compatible = "bst,c1200-sdhci";
+ reg = <0x0 0x22200000 0x0 0x1000>,
+ <0x0 0x23006000 0x0 0x1000>;
+ clocks = <&clk_mmc>;
+ clock-names = "core";
+ dma-coherent;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@32800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x32800000 0x0 0x10000>,
+ <0x0 0x32880000 0x0 0x100000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ always-on;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 8/9] arm64: defconfig: enable BST platform and SDHCI controller support
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
` (6 preceding siblings ...)
2025-09-23 6:10 ` [PATCH 7/9] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board Albert Yang
@ 2025-09-23 6:10 ` Albert Yang
2025-09-23 6:10 ` [PATCH 9/9] MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support Albert Yang
2025-09-25 7:06 ` [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Arnd Bergmann
9 siblings, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-09-23 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc,
Albert Yang
Enable support for Black Sesame Technologies (BST) platform and drivers
in the ARM64 defconfig:
- CONFIG_ARCH_BST: Enable BST SoC platform support
- CONFIG_MMC_SDHCI_BST: Enable BST C1200 DWCMSHC SDHCI controller driver
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
---
Changes for v4:
- move CONFIG_MMC_SDHCI_BST before CONFIG_MMC_SDHCI_F_SDH30
- Remove Signed-off-by line for Ge Gordon
- Simplify commit message (remove detailed description about eMMC/SD functionality)
Changes for v3:
- Also enable CONFIG_ARCH_BST in arm64 defconfig (in addition to CONFIG_MMC_SDHCI_BST)
Changes for v2:
- No changes
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 58f87d09366cd12ae212a1d107660afe8be6c5ef..91ad7911a2c2178581100d2ba41888b4b42fc87a 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -46,6 +46,7 @@ CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_BLAIZE=y
+CONFIG_ARCH_BST=y
CONFIG_ARCH_CIX=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_SPARX5=y
@@ -1196,6 +1197,7 @@ CONFIG_MMC_SDHCI_OF_SPARX5=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMC_SDHCI_BST=y
CONFIG_MMC_SDHCI_F_SDH30=y
CONFIG_MMC_MESON_GX=y
CONFIG_MMC_SDHCI_MSM=y
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH 9/9] MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
` (7 preceding siblings ...)
2025-09-23 6:10 ` [PATCH 8/9] arm64: defconfig: enable BST platform and SDHCI controller support Albert Yang
@ 2025-09-23 6:10 ` Albert Yang
2025-09-29 13:29 ` Adrian Hunter
2025-09-25 7:06 ` [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Arnd Bergmann
9 siblings, 1 reply; 25+ messages in thread
From: Albert Yang @ 2025-09-23 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ge Gordon,
BST Linux Kernel Upstream Group, Catalin Marinas, Will Deacon,
Ulf Hansson, Adrian Hunter, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc,
Albert Yang
Add a MAINTAINERS entry for Black Sesame Technologies (BST) ARM SoC
support. This entry covers device tree bindings, drivers, and board files
for BST SoCs, including MMC and platform support.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
---
Change for v4:
- Changed file name: sdhci-of-bst-c1200.c to sdhci-of-bst.c
- Changed title from "add and consolidate" to just "add"
- Simplified commit message description
- Removed Signed-off-by line for Ge Gordon
Change for v3:
- No changes
Change for v2:
- No changes
---
MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cd7ff55b5d321752ac44c91d2d7e74de28e08960..685294ef3e2ecf124219b2c5eafb8cad25600652 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2505,6 +2505,16 @@ S: Maintained
F: Documentation/devicetree/bindings/arm/blaize.yaml
F: arch/arm64/boot/dts/blaize/
+ARM/BST SOC SUPPORT
+M: Ge Gordon <gordon.ge@bst.ai>
+R: BST Linux Kernel Upstream Group <bst-upstream@bstai.top>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/arm/bst.yaml
+F: Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml
+F: arch/arm64/boot/dts/bst/
+F: drivers/mmc/host/sdhci-of-bst.c
+
ARM/CALXEDA HIGHBANK ARCHITECTURE
M: Andre Przywara <andre.przywara@arm.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
2.43.0
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 9/9] MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support
2025-09-23 6:10 ` [PATCH 9/9] MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support Albert Yang
@ 2025-09-29 13:29 ` Adrian Hunter
2025-10-15 7:30 ` Albert Yang
0 siblings, 1 reply; 25+ messages in thread
From: Adrian Hunter @ 2025-09-29 13:29 UTC (permalink / raw)
To: Albert Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ge Gordon, BST Linux Kernel Upstream Group, Catalin Marinas,
Will Deacon, Ulf Hansson, Arnd Bergmann
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mmc, soc
On 23/09/2025 09:10, Albert Yang wrote:
> Add a MAINTAINERS entry for Black Sesame Technologies (BST) ARM SoC
> support. This entry covers device tree bindings, drivers, and board files
> for BST SoCs, including MMC and platform support.
>
> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
> ---
> Change for v4:
> - Changed file name: sdhci-of-bst-c1200.c to sdhci-of-bst.c
> - Changed title from "add and consolidate" to just "add"
> - Simplified commit message description
> - Removed Signed-off-by line for Ge Gordon
>
> Change for v3:
> - No changes
>
> Change for v2:
> - No changes
> ---
> MAINTAINERS | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cd7ff55b5d321752ac44c91d2d7e74de28e08960..685294ef3e2ecf124219b2c5eafb8cad25600652 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2505,6 +2505,16 @@ S: Maintained
> F: Documentation/devicetree/bindings/arm/blaize.yaml
> F: arch/arm64/boot/dts/blaize/
>
> +ARM/BST SOC SUPPORT
> +M: Ge Gordon <gordon.ge@bst.ai>
> +R: BST Linux Kernel Upstream Group <bst-upstream@bstai.top>
> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +S: Maintained
Seems like it is "Supported" rather than "Maintained" ?
S: *Status*, one of the following:
Supported: Someone is actually paid to look after this.
Maintained: Someone actually looks after it.
Odd Fixes: It has a maintainer but they don't have time to do
much other than throw the odd patch in. See below..
Orphan: No current maintainer [but maybe you could take the
role as you write your new code].
Obsolete: Old code. Something tagged obsolete generally means
it has been replaced by a better system and you
should be using that.
> +F: Documentation/devicetree/bindings/arm/bst.yaml
> +F: Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml
> +F: arch/arm64/boot/dts/bst/
> +F: drivers/mmc/host/sdhci-of-bst.c
> +
> ARM/CALXEDA HIGHBANK ARCHITECTURE
> M: Andre Przywara <andre.przywara@arm.com>
> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 9/9] MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support
2025-09-29 13:29 ` Adrian Hunter
@ 2025-10-15 7:30 ` Albert Yang
0 siblings, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-10-15 7:30 UTC (permalink / raw)
To: adrian.hunter
Cc: arnd, bst-upstream, catalin.marinas, conor+dt, devicetree,
gordon.ge, krzk+dt, linux-arm-kernel, linux-kernel, linux-mmc,
robh, soc, ulf.hansson, will, yangzh0906
Hi Adrian,
Thank you for the review and feedback!
On Mon, Sep 29, 2025 at 04:29:25PM +0300, Adrian Hunter wrote:
> On 23/09/2025 09:10, Albert Yang wrote:
> > +ARM/BST SOC SUPPORT
> > +M: Ge Gordon <gordon.ge@bst.ai>
> > +R: BST Linux Kernel Upstream Group <bst-upstream@bstai.top>
> > +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> > +S: Maintained
>
> Seems like it is "Supported" rather than "Maintained" ?
>
> S: *Status*, one of the following:
> Supported: Someone is actually paid to look after this.
> Maintained: Someone actually looks after it.
> Odd Fixes: It has a maintainer but they don't have time to do
> much other than throw the odd patch in. See below..
> Orphan: No current maintainer [but maybe you could take the
> role as you write your new code].
> Obsolete: Old code. Something tagged obsolete generally means
> it has been replaced by a better system and you
> should be using that.> The status should likely be "Supported" rather than "Maintained"
> based on the MAINTAINERS guidelines.
You're absolutely right. "Supported" is more appropriate for this
vendor-supported hardware. I will update the STATUS field to
"Supported" in next of the patch series.
Thanks for pointing this out.
Best regards,
Albert Yang
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board
2025-09-23 6:10 [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Albert Yang
` (8 preceding siblings ...)
2025-09-23 6:10 ` [PATCH 9/9] MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support Albert Yang
@ 2025-09-25 7:06 ` Arnd Bergmann
2025-09-25 9:03 ` Albert Yang
9 siblings, 1 reply; 25+ messages in thread
From: Arnd Bergmann @ 2025-09-25 7:06 UTC (permalink / raw)
To: yangzh0906@thundersoft.com, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, gordon.ge, bst-upstream, Catalin Marinas,
Will Deacon, Ulf Hansson, Adrian Hunter
Cc: devicetree, linux-kernel, linux-arm-kernel,
linux-mmc @ vger . kernel . org, soc, Krzysztof Kozlowski
On Tue, Sep 23, 2025, at 08:10, Albert Yang wrote:
> This patch series introduces comprehensive support for Black Sesame
> Technologies
> (BST) C1200 SoC and CDCU1.0 ADAS 4C2G board. BST is a leading
> automotive-grade
> computing SoC provider focusing on intelligent driving, computer
> vision, and AI
> capabilities for ADAS and autonomous driving applications. You can find
> more information
> about the SoC and related boards at: https://bst.ai
Hi Albert,
I see you submitted the series to soc@lists.linux.dev, which would
normally indicate that it has been fully reviewed and is ready
to be merged.
I'd be happy to merge the actual SoC portions in arch/arm64 as they
do seem to be ready, and for a new SoC support I sometimes merge
in required driver changes with a subsystem (uart, irqchip, clk, ...)
maintainer's Ack as well. However the MMC driver portions in patches
4-6 don't really fall into that category, as there has not been
any Ack for this version yet, and MMC is not one of the subsystems
we normally make this exception for.
Given the current timing, I would suggest that you respin the
series for 6.19 once 6.18-rc1 is out and leave out those three
patches in the submission to soc@lists.linux.dev.
If the MMC driver gets merged for 6.19, it's ok to keep the
sdhci device nodes in the dtsi file here, but to make things
easier, you can also leave out those nodes in the initial
submission and send this as a follow-up patch to
soc@lists.linux.dev once the driver is actually merged.
Arnd
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board
2025-09-25 7:06 ` [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board Arnd Bergmann
@ 2025-09-25 9:03 ` Albert Yang
2025-09-25 12:11 ` Albert Yang
0 siblings, 1 reply; 25+ messages in thread
From: Albert Yang @ 2025-09-25 9:03 UTC (permalink / raw)
To: arnd
Cc: adrian.hunter, bst-upstream, catalin.marinas, conor+dt,
devicetree, gordon.ge, krzk+dt, krzysztof.kozlowski,
linux-arm-kernel, linux-kernel, linux-mmc, robh, soc, ulf.hansson,
will, yangzh0906
Hi Arnd,
Thanks a lot for the clear guidance and for looking at the series.
You are absolutely right about the soc@lists.linux.dev submission. The
inclusion was an unintended side effect of using:
b4 prep --auto-to-cc
I mistakenly trusted the automatically generated list without pruning it.
I'll manually adjust the To/Cc going forward and only add soc@lists.linux.dev
once the SoC base is ready for your tree.
> I'd be happy to merge the actual SoC portions in arch/arm64 as they
> do seem to be ready, and for a new SoC support I sometimes merge
> in required driver changes with a subsystem (uart, irqchip, clk, ...)
> maintainer's Ack as well. However the MMC driver portions in patches
> 4-6 don't really fall into that category, as there has not been
> any Ack for this version yet, and MMC is not one of the subsystems
> we normally make this exception for.
Understood. Not all patches in the series have Acked-by/Reviewed-by yet
(especially the MMC related ones), so I'll restructure for v5 per your
recommendation instead of waiting for every Ack before resubmitting.
> Given the current timing, I would suggest that you respin the
> series for 6.19 once 6.18-rc1 is out and leave out those three
> patches in the submission to soc@lists.linux.dev.
Will do. Planned split for v5:
Series A (SoC foundation) -> target: arm-soc (NOT including MMC driver patches)
1. Vendor prefix dt-binding
2. SoC / board dt-bindings
3. ARCH_BST Kconfig/Makefile enablement
4. Initial dtsi/dts (without the sdhci/mmc nodes, see note below)
5. MAINTAINERS entry
6. (Optional/minimal) defconfig updates – avoiding enabling symbols
that rely on not-yet-merged drivers
Separate MMC series -> target: linux-mmc (cc: devicetree, you, lists)
a. MMC controller dt-binding (current patch 4)
b. MMC driver patches (current patches 5–6)
> If the MMC driver gets merged for 6.19, it's ok to keep the
> sdhci device nodes in the dtsi file here, but to make things
> easier, you can also leave out those nodes in the initial
> submission and send this as a follow-up patch to
> soc@lists.linux.dev once the driver is actually merged.
My preference is to OMIT the sdhci/mmc nodes entirely in v5 to keep the
base SoC description minimal and avoid orphan nodes. If you would rather
I keep them present but with status = "disabled", please let me know and
I will adjust accordingly before sending.
After the MMC driver lands, I'll send a follow-up patch adding the
sdhci/mmc nodes to the SoC dtsi.
I will also:
- Ensure vendor prefix binding precedes its usage
- Trim any defconfig entries referencing the unmerged driver
- Remove soc@lists.linux.dev from To/Cc until the SoC subset is
really intended for your tree
Does this split and sequencing match your expectations? Any further
adjustments you'd like before I prepare v5?
Thanks again for the review and direction.
--
Best regards,
Albert Yang
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board
2025-09-25 9:03 ` Albert Yang
@ 2025-09-25 12:11 ` Albert Yang
2025-09-25 13:34 ` Ulf Hansson
0 siblings, 1 reply; 25+ messages in thread
From: Albert Yang @ 2025-09-25 12:11 UTC (permalink / raw)
To: arnd
Cc: adrian.hunter, bst-upstream, catalin.marinas, conor+dt,
devicetree, gordon.ge, krzk+dt, krzysztof.kozlowski,
linux-arm-kernel, linux-kernel, linux-mmc, robh, ulf.hansson,
will, yangzh0906
On Thu, Sep 25, 2025 at 05:03:57PM +0800, Albert Yang wrote:Subject: Re: [PATCH] splitting SoC and MMC parts
Hi Arnd,
I may have missed an important detail in my previous note. If I split
out the MMC-related patches and submit only the SoC parts first, I
cannot validate the SoC on real hardware: both the kernel and the root
filesystem live on the MMC device. Without the MMC stack (DT bindings
and the controller driver), the board does not boot to userspace, so I
cannot properly verify the SoC/DT changes in isolation.
Would you prefer that I:
- keep the MMC pieces in the same series for initial bring-up; or
- validate everything locally, then send only the SoC/DT parts first and
follow up with the MMC binding/driver as a separate series?
I’m not entirely sure which approach best matches the normal workflow,
so your guidance would be appreciated. I can proceed whichever way you
think is most appropriate.
Thanks for the review and suggestions.
Best regards,
Albert
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board
2025-09-25 12:11 ` Albert Yang
@ 2025-09-25 13:34 ` Ulf Hansson
2025-09-25 13:38 ` Arnd Bergmann
0 siblings, 1 reply; 25+ messages in thread
From: Ulf Hansson @ 2025-09-25 13:34 UTC (permalink / raw)
To: Albert Yang
Cc: arnd, adrian.hunter, bst-upstream, catalin.marinas, conor+dt,
devicetree, gordon.ge, krzk+dt, krzysztof.kozlowski,
linux-arm-kernel, linux-kernel, linux-mmc, robh, will
On Thu, 25 Sept 2025 at 14:12, Albert Yang <yangzh0906@thundersoft.com> wrote:
>
> On Thu, Sep 25, 2025 at 05:03:57PM +0800, Albert Yang wrote:Subject: Re: [PATCH] splitting SoC and MMC parts
>
> Hi Arnd,
>
> I may have missed an important detail in my previous note. If I split
> out the MMC-related patches and submit only the SoC parts first, I
> cannot validate the SoC on real hardware: both the kernel and the root
> filesystem live on the MMC device. Without the MMC stack (DT bindings
> and the controller driver), the board does not boot to userspace, so I
> cannot properly verify the SoC/DT changes in isolation.
At least to me, I would not consider that a problem. As long as you
can test the pieces together "manually" that's fine, I think.
I mean, the platform was not supported in the first place, so it's not
like we would be introducing a regression - or break something, right?
>
> Would you prefer that I:
> - keep the MMC pieces in the same series for initial bring-up; or
> - validate everything locally, then send only the SoC/DT parts first and
> follow up with the MMC binding/driver as a separate series?
>
> I’m not entirely sure which approach best matches the normal workflow,
> so your guidance would be appreciated. I can proceed whichever way you
> think is most appropriate.
I think doing things in parallel would be the best/fastest way
forward. Validating locally and sending the pieces upstream to
different subsystems.
>
> Thanks for the review and suggestions.
>
> Best regards,
> Albert
Kind regards
Uffe
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board
2025-09-25 13:34 ` Ulf Hansson
@ 2025-09-25 13:38 ` Arnd Bergmann
2025-09-26 1:48 ` Albert Yang
0 siblings, 1 reply; 25+ messages in thread
From: Arnd Bergmann @ 2025-09-25 13:38 UTC (permalink / raw)
To: Ulf Hansson, yangzh0906@thundersoft.com
Cc: Adrian Hunter, bst-upstream, Catalin Marinas, Conor Dooley,
devicetree, gordon.ge, krzk+dt, Krzysztof Kozlowski,
linux-arm-kernel, linux-kernel, linux-mmc @ vger . kernel . org,
Rob Herring, Will Deacon
On Thu, Sep 25, 2025, at 15:34, Ulf Hansson wrote:
> On Thu, 25 Sept 2025 at 14:12, Albert Yang <yangzh0906@thundersoft.com> wrote:
>> On Thu, Sep 25, 2025 at 05:03:57PM +0800, Albert Yang wrote:
>> Subject: Re: [PATCH] splitting SoC and MMC parts
>>
>> Hi Arnd,
>>
>> I may have missed an important detail in my previous note. If I split
>> out the MMC-related patches and submit only the SoC parts first, I
>> cannot validate the SoC on real hardware: both the kernel and the root
>> filesystem live on the MMC device. Without the MMC stack (DT bindings
>> and the controller driver), the board does not boot to userspace, so I
>> cannot properly verify the SoC/DT changes in isolation.
>
> At least to me, I would not consider that a problem. As long as you
> can test the pieces together "manually" that's fine, I think.
>
> I mean, the platform was not supported in the first place, so it's not
> like we would be introducing a regression - or break something, right?
Agreed, it's rare for newly added platforms to immediately have
everything working, and we can still fix things if they don't.
It's also possible to test userspace by using a standalone
initramfs with a login shell or an automated test suite, but
I don't require that.
Arnd
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 0/9] arm64: introduce Black Sesame Technologies C1200 SoC and CDCU1.0 board
2025-09-25 13:38 ` Arnd Bergmann
@ 2025-09-26 1:48 ` Albert Yang
0 siblings, 0 replies; 25+ messages in thread
From: Albert Yang @ 2025-09-26 1:48 UTC (permalink / raw)
To: arnd
Cc: adrian.hunter, bst-upstream, catalin.marinas, conor+dt,
devicetree, gordon.ge, krzk+dt, krzysztof.kozlowski,
linux-arm-kernel, linux-kernel, linux-mmc, robh, ulf.hansson,
will, yangzh0906
On Thu, Sep 25, 2025 at 03:38:44PM +0200, Arnd Bergmann wrote:
> On Thu, Sep 25, 2025, at 15:34, Ulf Hansson wrote:
> > On Thu, 25 Sept 2025 at 14:12, Albert Yang <yangzh0906@thundersoft.com> wrote:
> >> On Thu, Sep 25, 2025 at 05:03:57PM +0800, Albert Yang wrote:
> >>
> >> Hi Arnd,
> >>
> >> I may have missed an important detail in my previous note. If I split
> >> out the MMC-related patches and submit only the SoC parts first, I
> >> cannot validate the SoC on real hardware: both the kernel and the root
> >> filesystem live on the MMC device. Without the MMC stack (DT bindings
> >> and the controller driver), the board does not boot to userspace, so I
> >> cannot properly verify the SoC/DT changes in isolation.
> >
> > At least to me, I would not consider that a problem. As long as you
> > can test the pieces together "manually" that's fine, I think.
> >
> > I mean, the platform was not supported in the first place, so it's not
> > like we would be introducing a regression - or break something, right?
>
> Agreed, it's rare for newly added platforms to immediately have
> everything working, and we can still fix things if they don't.
>
> It's also possible to test userspace by using a standalone
> initramfs with a login shell or an automated test suite, but
> I don't require that.
Hi Arnd, Ulf,
Thank you both for the clarifications.
Understood regarding validation expectations. I'll proceed with the split:
* v5 SoC series (no MMC binding/driver, no mmc nodes in dtsi)
* Separate MMC series (binding + driver) to linux-mmc
* Follow-up enable patch once the driver lands
If any critical fix is found while iterating on the MMC series, I'll send
a follow-up patch depending on timing.
I'll move ahead with preparing v5 accordingly.
Thanks again for the guidance.
Best regards,
Albert Yang
^ permalink raw reply [flat|nested] 25+ messages in thread